公开(公告)号：DE60030386T2

公开(公告)日：2007-09-13

申请号：DE60030386

申请日：2000-10-30

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ALERS GLENN B

IPC: H01L21/02 ,  H01L27/04 ,  H01L21/283 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/321 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L29/78

Abstract: An electronic device having a capacitor structure is formed by depositing a metal layer defining a first electrode on a film of high dielectric constant material, and then depositing the dielectric layer of the capacitor structure on the first electrode. This resulting structure is then exposed to a nitrogen plasma and the top electrode is formed. Exposing the first electrode to a plasma of pure nitrogen prevents the partial oxidation of the first electrode and reduces the density of charge traps at the electrode/dielectric interface. The dielectric film is passivated with the nitrogen material before forming the top electrode to prevent interdiffusion between the electrode and the dielectric.

公开(公告)号：DE60023573D1

公开(公告)日：2005-12-08

申请号：DE60023573

申请日：2000-01-06

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ALERS GLENN B ,  ROY PRADIP KUMAR

IPC: H01L27/04 ,  H01L21/02 ,  H01L21/316 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/3105 ,  C23C16/40 ,  C23C16/56

Abstract: A method for making an integrated circuit capacitor which in one embodiment preferably comprises the steps of: forming, adjacent a semiconductor substrate, a first metal electrode comprising a metal nitride surface portion; forming a tantalum pentoxide layer on the metal nitride surface portion while maintaining a temperature below an oxidizing temperature of the metal; remote plasma annealing the tantalum pentoxide layer; and forming a second electrode adjacent the tantalum pentoxide layer. The step of forming the tantalum pentoxide layer preferably comprises chemical vapor deposition of the tantalum pentoxide at a temperature below about 500 DEG C. Accordingly, oxidation of the metal is avoided and a high quality tantalum pentoxide is produced. The metal of the first metal electrode may comprise at least one of titanium, tungsten, tantalum, and alloys thereof.

公开(公告)号：DE60023573T2

公开(公告)日：2006-07-27

申请号：DE60023573

申请日：2000-01-06

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ALERS GLENN B ,  ROY PRADIP KUMAR

IPC: H01L21/316 ,  H01L27/04 ,  C23C16/40 ,  C23C16/56 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: A method for making an integrated circuit capacitor which in one embodiment preferably comprises the steps of: forming, adjacent a semiconductor substrate, a first metal electrode comprising a metal nitride surface portion; forming a tantalum pentoxide layer on the metal nitride surface portion while maintaining a temperature below an oxidizing temperature of the metal; remote plasma annealing the tantalum pentoxide layer; and forming a second electrode adjacent the tantalum pentoxide layer. The step of forming the tantalum pentoxide layer preferably comprises chemical vapor deposition of the tantalum pentoxide at a temperature below about 500 DEG C. Accordingly, oxidation of the metal is avoided and a high quality tantalum pentoxide is produced. The metal of the first metal electrode may comprise at least one of titanium, tungsten, tantalum, and alloys thereof.

公开(公告)号：GB2350929B

公开(公告)日：2002-05-22

申请号：GB0009611

申请日：2000-04-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： VITKAVAGE DANIEL JOSEPH ,  ALERS GLENN B ,  LEE TSENG-CHUNG ,  MAYNARD HELEN LOUISE

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: A capacitor structure is formed in a window in a dielectric layer of an integrated circuit. The lower electrode (or plate) is disposed on a portion side surface of the cavity but not on the top surface of the dielectric. A layer of dielectric material is disposed on the lower electrode and upon the top surface of the integrated circuit dielectric. Finally, an upper electrode (or plate) is disposed on the layer of dielectric material. Because the lower electrode is removed from a portion of the cavity sidewall and top surface of the dielectric shorting problems which could result during planarization are avoided. A technique for fabricating an integrated circuit (IC) for use in multi-level structures is also disclosed. The technique is readily incorporated into standard multi-level processing techniques. After a window is opened in the particular dielectric layer of the IC, a conductive layer is deposited in the window and forms the lower plate of a capacitor. The lower plate is then etched so that it is removed from a portion of the sidewalls and from the top surface of the dielectric layer. After the lower electrode is etched, a dielectric material is disposed in the cavity and on the top surface of the dielectric layer. A second layer of conductor is disposed on top of the dielectric material layer, thus completing the capacitor structure.

公开(公告)号：DE60030386D1

公开(公告)日：2006-10-12

申请号：DE60030386

申请日：2000-10-30

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ALERS GLENN B

IPC: H01L21/02 ,  H01L27/04 ,  H01L21/283 ,  H01L21/3105 ,  H01L21/316 ,  H01L21/321 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/06 ,  H01L27/108 ,  H01L29/78

Abstract: An electronic device having a capacitor structure is formed by depositing a metal layer defining a first electrode on a film of high dielectric constant material, and then depositing the dielectric layer of the capacitor structure on the first electrode. This resulting structure is then exposed to a nitrogen plasma and the top electrode is formed. Exposing the first electrode to a plasma of pure nitrogen prevents the partial oxidation of the first electrode and reduces the density of charge traps at the electrode/dielectric interface. The dielectric film is passivated with the nitrogen material before forming the top electrode to prevent interdiffusion between the electrode and the dielectric.

公开(公告)号：GB2350929A

公开(公告)日：2000-12-13

申请号：GB0009611

申请日：2000-04-18

Applicant: LUCENT TECHNOLOGIES INC

Inventor： VITKAVAGE DANIEL JOSEPH ,  ALERS GLENN B ,  LEE TSENG-CHUNG ,  MAYNARD HELEN LOUISE

IPC: H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108

Abstract: A capacitor structure situated in window (101, Fig. 1) of dielectric layer (D 2 ) of an integrated circuit comprises lower electrode (102), dielectric layer (405) and upper electrode (406). The lower electrode (102) is disposed on side surface of cavity (101, Fig. 1), but not on the top surface of layer (D 2 ), and the top end of the lower electrode (102) is preferably about 0.2 microns below the top surface of the layer (D 2 ). The lower electrode (102) may be in contact with conductive plug (609), and the dielectric layer (405) is preferably tantalum oxide. A process for fabricating an integrated circuit is also disclosed, where lower capacitor plate (102) is deposited on both the sidewalls of the opening and the top surface of layer (D 2 ), and then the lower plate (102) is etched from the top surface and a portion of the sidewalls.

公开(公告)号：AU2411300A

公开(公告)日：2000-08-01

申请号：AU2411300

申请日：2000-01-11

Applicant: LUCENT TECHNOLOGIES INC

Inventor： ALERS GLENN B ,  MERCHANT SAILESH M ,  ROY PRADIP K

IPC: H01L21/02 ,  H01L21/316 ,  H01L29/49 ,  H01L29/92

Abstract: The present invention provides a semiconductor device that has a metal barrier layer for a dielectric material, which can be used in an integrated circuit, if so desired. The semiconductor device provides a capacitance to the integrated circuit and in a preferred embodiment comprises a first layer located on a surface of the integrated circuit. A metal barrier layer is located on the first layer and is susceptible to oxidation by oxygen. A high K capacitor dielectric layer (i.e., a higher K than silicon dioxide) that contains oxygen, such as tantalum pentoxide, is located over the metal barrier layer. The semiconductor device further includes a first layer located over the high K capacitor dielectric layer.