公开(公告)号：DE60038423D1

公开(公告)日：2008-05-08

申请号：DE60038423

申请日：2000-10-16

Applicant: LUCENT TECHNOLOGIES INC

Inventor： LAYADI NACE ,  MERCHANT SAILESH MANSINH ,  MOLLOY SIMON JOHN ,  ROY PRADIP KUMAR

IPC: H01L21/302 ,  H01L21/768 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L23/522

Abstract: A method for making a semiconductor device (10) includes the steps of forming a first conductive layer (50) adjacent a substrate (52), forming an etch stop layer (54) on the conductive layer, and forming a dielectric layer (56) on the etch stop layer. The dielectric layer includes a material having a low dielectric constant, and a via (12) is formed through the dielectric layer to expose the etch stop layer at the bottom, with porous sidewalls (16) being produced. The exposed etch stop layer (54) is etched using an etchant that cooperates with etched material from the etch stop layer to form a polymeric layer (64) to coat the porous sidewalls of the via. Since the etchant cooperates with the etched material from the etch stop layer to form the polymeric layer coating the porous sidewalls of the via, a separate coating layer deposition step is not required after the via is etched and cleaned. After the porous sidewalls have been coated and polymeric material has been etched from the bottom of the via, a barrier metal layer (66) is formed on the polymeric layer (64), a seed layer (68) is formed on the barrier metal layer, and a second conductive layer (70) is formed on the seed layer contacting the first conductive layer in the via.

公开(公告)号：GB2363677B

公开(公告)日：2003-09-10

申请号：GB0028872

申请日：2000-11-27

Applicant: LUCENT TECHNOLOGIES INC

Inventor： BOULIN DAVID M ,  FARROW REGINALD C ,  KILILYALLI ISIK C ,  MKRTCHYAN MASIS ,  LAYADI NACE

IPC: G03F7/20 ,  G03F9/00 ,  H01J37/304 ,  H01J37/305 ,  H01L21/027 ,  H01L23/544

Abstract: A multi-layered semiconductor structure having an alignment feature for aligning a lithography mask and that may be used in connection with a SCALPEL tool. The present invention is particularly well-suited for sub-micron CMOS technology devices and circuits, but is not limited thereto. The present invention advantageously permits use of an electron beam source for both alignment and exposure of a lithography mask on a semiconductor wafer. The present invention also advantageously enables the formation of an alignment feature early (i.e., zero-level) in the semiconductor device fabrication process.

公开(公告)号：GB2363677A

公开(公告)日：2002-01-02

申请号：GB0028872

申请日：2000-11-27

Applicant: LUCENT TECHNOLOGIES INC

Inventor： BOULIN DAVID M ,  FARROW REGINALD C ,  KILILYALLI ISIK C ,  MKRTCHYAN MASIS ,  LAYADI NACE

IPC: G03F7/20 ,  G03F9/00 ,  H01J37/304 ,  H01J37/305 ,  H01L21/027 ,  H01L23/544

Abstract: A method of forming a multi-layered semiconductor structure having substrate (20) comprises the steps of forming an alignment feature (60) in or on substrate (20), and aligning lithography mask (140) using alignment feature (60) with a Scattering with Angular Limitation in Projection Electron-beam Lithography (SCALPEL) tool (100) having an electron beam source (110) for directing an electron beam toward semiconductor structure (10). The alignment feature (60) is detected as it backscatters a greater amount of electrons than the surrounding substrate (20). This information may then be used to align lithography mask (140). The alignment feature (60) may include shallow trench (22, Fig. 1) containing silicon dioxide (30) and a high atomic number material (50) selected from tungsten, tantalum, cobalt, titanium, or the silicides and nitrides of these metals. The alignment feature (60) may be formed in a polysilicon layer on a silicon dioxide layer.

公开(公告)号：GB2345794B

公开(公告)日：2001-04-04

申请号：GB0000741

申请日：2000-01-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： FRITZINGER LARRY BRUCE ,  LAYADI NACE ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP KUMAR

IPC: H01L21/02 ,  H01G4/33 ,  H01L21/285 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

Abstract: The present invention provides an integrated circuit capacitor comprising a conductive plug comprising a top portion comprising sidewalls, and a bottom portion, wherein the bottom portion of the plug is coated with a material selected from the group consisting of titanium and titanium nitride and wherein the top portion of the plug is substantially not coated with a material selected from the group consisting of titanium and titanium nitride.

公开(公告)号：GB2345793A

公开(公告)日：2000-07-19

申请号：GB0000739

申请日：2000-01-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： FRITZINGER LARRY BRUCE ,  LAYADI NACE ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP KUMAR

IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/285 ,  H01L27/108

Abstract: A capacitor for an integrated circuit, eg a DRAM comprises a conductive plug 7 with sidewalls formed form layers of TiN and or Ti, 3, 5. An electrode material 9 which does not comprise Ti or TiN is coated over the conductive plug 7, prior to the formation of the dielectric layer 11 and the upper electrode 13. Preferably, the electrode material 9 comprises tungsten, and the dielectric layer 11 is tantalum pentoxide. The arrangement eliminates contact between the dielectric 11 and the titanium containing layers 5, 3 resulting in a lower leakage current for the device.