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    CAPACITOR FOR INTEGRATED CIRCUIT
    2.
    发明专利
    CAPACITOR FOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JP2000294746A

    公开(公告)日：2000-10-20

    申请号：JP2000004788

    申请日：2000-01-13

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： FRITZINGER LARRY BRUCE ,  LAYADI NACE ,  MERCHANT SAILESH M ,  ROY PRADIP K

    IPC: H01L21/8242 ,  H01L21/02 ,  H01L21/285 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To obtain a compact capacitor that solves a problem regarding a leakage current or other problems. SOLUTION: The capacitor for an integrated circuit is composed of a conductive plug 7 with an upper surface and an exposed sidewall, and an electrode layer 9 formed on the sidewall of the conductive plug 7. Then, the above side wall includes a layer 3 or 5 made of a material selected form a group consisting of titanium(Ti) and titanium nitride(TiN), and the material of the electrode layer 8 contains neither titanium(Ti) not the titanium nitride(TiN).

    Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
    3.
    发明专利
    Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics 未知

    公开(公告)号：GB2359661B

    公开(公告)日：2002-11-20

    申请号：GB0019483

    申请日：2000-08-08

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： ABDELGADIR MAHJOUB ALI ,  LAYADI NACE ,  MERCHANT SAILESH MANSINH ,  SAXENA VIVEK ,  YIH PEI H

    IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiOx, where x is preferably less than 2.

    5.
    发明专利
    未知

    公开(公告)号：DE60038423T2

    公开(公告)日：2009-04-23

    申请号：DE60038423

    申请日：2000-10-16

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： LAYADI NACE ,  MERCHANT SAILESH MANSINH ,  MOLLOY SIMON JOHN ,  ROY PRADIP KUMAR

    IPC: H01L21/302 ,  H01L21/768 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L23/522

    Abstract: A method for making a semiconductor device (10) includes the steps of forming a first conductive layer (50) adjacent a substrate (52), forming an etch stop layer (54) on the conductive layer, and forming a dielectric layer (56) on the etch stop layer. The dielectric layer includes a material having a low dielectric constant, and a via (12) is formed through the dielectric layer to expose the etch stop layer at the bottom, with porous sidewalls (16) being produced. The exposed etch stop layer (54) is etched using an etchant that cooperates with etched material from the etch stop layer to form a polymeric layer (64) to coat the porous sidewalls of the via. Since the etchant cooperates with the etched material from the etch stop layer to form the polymeric layer coating the porous sidewalls of the via, a separate coating layer deposition step is not required after the via is etched and cleaned. After the porous sidewalls have been coated and polymeric material has been etched from the bottom of the via, a barrier metal layer (66) is formed on the polymeric layer (64), a seed layer (68) is formed on the barrier metal layer, and a second conductive layer (70) is formed on the seed layer contacting the first conductive layer in the via.

    Method of forming an alignment feature in or on a multi-layered semiconductor structure
    6.
    发明专利
    Method of forming an alignment feature in or on a multi-layered semiconductor structure 未知

    公开(公告)号：GB2372150A

    公开(公告)日：2002-08-14

    申请号：GB0211288

    申请日：2000-11-27

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： BOULIN DAVID M ,  FARROW REGINALD C ,  KIZILYALLI ISIK C ,  MKRTCHYAN MASIS ,  LAYADI NACE

    IPC: H01J37/304 ,  H01L23/544

    Abstract: A method of forming a multi-layered semiconductor structure having substrate (20) comprises the steps of forming an alignment feature (60) in or on substrate (20), and aligning lithography mask (140) using alignment feature (60) with a Scattering with Angular Limitation in Projection Electron-beam Lithography (SCALPEL) tool (100) having an electron beam source (110) for directing an electron beam toward semiconductor structure (10). The alignment feature (60) is detected as it backscatters a greater amount of electrons than the surrounding substrate (20). This information may then be used to align lithography mask (140). The alignment feature (60) may include shallow trench (22, Fig. 1) containing silicon dioxide (30) and a high atomic number material (50) selected from tungsten, tantalum, cobalt, titanium, or the silicides and nitrides of these metals. The alignment feature (60) may be formed in a polysilicon layer on a silicon dioxide layer.

    Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics
    9.
    发明专利
    Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics 未知

    公开(公告)号：GB2359661A

    公开(公告)日：2001-08-29

    申请号：GB0019483

    申请日：2000-08-08

    Applicant: LUCENT TECHNOLOGIES INC

    Inventor： ABDELGADIR MAHJOUB ALI ,  LAYADI NACE ,  MERCHANT SAILESH MANSINH ,  SAXENA VIVEK ,  YIH PEI H

    IPC: H01L21/3205 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

    Abstract: A cap or barrier that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit may be fabricated by disposing the diffusion-preventing barrier layer (104) between a first dielectric layer (103) and the conductive layer (201) at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiO x , where x is preferably less than 2 and the first dielectric layer is fluorosilicate glass (FSG).

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