公开(公告)号：JPH1174214A

公开(公告)日：1999-03-16

申请号：JP17827098

申请日：1998-06-25

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MA YI ,  ROY PRADIP K

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/51

Abstract: PROBLEM TO BE SOLVED: To form a region that is strong against the damage of nitrogen oxide and to improve the reliability and life of a device by injecting nitrogen ions into source/drain regions at an inclined angle and thermally annealing the resultant structure. SOLUTION: A region 16 located below a gate becomes the channel of the transistor, and a source region 17 and a drain region 18 are located at both sides of the channel. Then, nitrogen is injected into the source and drain regions 17 and 18 at an inclination angle of ϕ. A material is thermally annealed succeeding implanting of ions. As a result of thermal annealing, the damage of ion implantation is eliminated, then, the implanted nitrogen are desorbed toward an interface and forms the protection layer of nitrogen oxide near the interface between a dielectric/source and a dielectric/drain. Finally, a contact to the source, gate, and drain is formed, thus completing a field effect device.

公开(公告)号：GB2351844A

公开(公告)日：2001-01-10

申请号：GB0014433

申请日：2000-06-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MA YI ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP KUMAR

IPC: H01L21/336 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/94 ,  H01L21/283

Abstract: An integrated circuit has a dielectric material layer 102, 103 disposed over a substrate 101. The dielectric layer 102, 103 has an equivalent electrical thickness of 2.5 nm or less, relative to silicon dioxide. The dielectric material 102, 103, includes at least one layer other than silicon dioxide. There is an electrode 104 which may consist of W, W x Si y , WSi x N y , TaSi x N y , MoSi x N y , Ma, Ta, or Ti, disposed over the dielectric layer 102, 103. The dielectric layer 102, 103 may comprise an oxide layer 102 grown on the substrate 101 and a high-k dielectric material 103. The high-k dielectric may be Ta 2 O 5 , ZrO 2 , TiO 2 or a pervoskite material, which can be disposed on the grown oxide layer 102. The substrate 101 may be an oxidizable layer, and a stress free oxide layer 105 may be disposed between the oxidizable layer 101 and the grown oxide layer 102. The high-k dielectric layer 103 may be doped with nitrogen. The integrated circuit may be a DRAM, FLASH, or an analog or mixed signal CMOS circuit.

公开(公告)号：GB2356739B

公开(公告)日：2002-04-17

申请号：GB0019481

申请日：2000-08-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MA YI ,  YEN ALLEN

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423

Abstract: A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region. The method further includes the step of removing the masking implant layer after the implanting to expose the channel region. A silicon epitaxial layer is formed on the exposed channel region, and at least a portion of the silicon epitaxial layer is converted to silicon oxide to define a gate dielectric layer for the transistor. The gate dielectric layer includes a gate oxide layer, and a silicon protection layer between the gate oxide layer and the channel region. A conductive gate is formed on an upper surface of the gate oxide layer. Since the gate dielectric layer does not include germanium, a stable gate dielectric layer is provided for the high speed silicon-germanium transistor.

公开(公告)号：GB2351844B

公开(公告)日：2002-03-20

申请号：GB0014433

申请日：2000-06-13

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KIZILYALLI ISIK C ,  MA YI ,  MERCHANT SAILESH MANSINH ,  ROY PRADIP KUMAR

IPC: H01L21/336 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51 ,  H01L29/94 ,  H01L21/283

Abstract: The present invention relates to a gate stack structure having a dielectric material layer disposed on a substrate with a gate electrode disposed thereon. In an exemplary embodiment, the dielectric material layer has an equivalent electrical thickness of 2.2 nm or less and includes at least one layer other than silicon dioxide. Furthermore, the dielectric material layer of the present invention enables device scaling and provides (1) decreased leakage current and improved tunneling voltage compared to a conventional gate dielectric; and (2) avoids the perils of ultra-thin silicon dioxide when used exclusively as the gate dielectric.

公开(公告)号：GB2362029A

公开(公告)日：2001-11-07

申请号：GB0025340

申请日：2000-10-16

Applicant: LUCENT TECHNOLOGIES INC

Inventor： KANE BRITTIN CHARLES ,  LAUGHERY MICHAEL A ,  MA YI

IPC: H01L29/78 ,  H01L21/335 ,  H01L21/336 ,  H01L29/49 ,  H01L21/28 ,  H01L29/423

Abstract: A multi-layer spacer is formed adjacent a gate 301 of a FET structure. The multi-layer spacer includes a layer of low-k material 306 which reduces parasitic capacitance, and a layer of material which enables etch selectivity relative 307 to the substrate 101 and isolation oxides 301. The process helps avoid over-etching of active and isolation regions. The layers are preferably porous or carbon doped silicon dioxide 306 and silicon nitride 307. The transistor may be a lightly doped drain (LLD) structure.

公开(公告)号：GB2356739A

公开(公告)日：2001-05-30

申请号：GB0019481

申请日：2000-08-08

Applicant: LUCENT TECHNOLOGIES INC

Inventor： MA YI ,  YEN ALLEN

IPC: H01L29/78 ,  H01L21/20 ,  H01L21/28 ,  H01L21/316 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423

Abstract: A method for making a transistor includes the steps of providing a silicon substrate including a silicon-germanium epitaxial layer, forming a masking implant layer on a channel region of the silicon-germanium epitaxial layer, and implanting dopants into the silicon-germanium epitaxial layer using the masking implant layer to define spaced apart source and drain regions adjacent the channel region. The method further includes the step of removing the masking implant layer after the implanting to expose the channel region. A silicon epitaxial layer is formed on the exposed channel region, and at least a portion of the silicon epitaxial layer is converted to silicon oxide to define a gate dielectric layer for the transistor. The gate dielectric layer includes a gate oxide layer, and a silicon protection layer between the gate oxide layer and the channel region. A conductive gate is formed on an upper surface of the gate oxide layer. Since the gate dielectric layer does not include germanium, a stable gate dielectric layer is provided for the high speed silicon-germanium transistor.