PREPARATION OF SEMICONDUCTOR STRUCTURE HAVING METALLIC OXIDE INTERFACE WITH SILICON

    公开(公告)号:JP2001068467A

    公开(公告)日:2001-03-16

    申请号:JP2000213906

    申请日:2000-07-14

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide a thin and stable crystalline silicate interface with silicon by forming a seed layer formed of a silicate crystalline material on the surface of a silicon substrate and forming a high dielectric oxide layer on the seed layer. SOLUTION: A substrate 10 is heated properly and the surface of the substrate 10 having SiO layer thereon is exposed to a metallic beam 18 such as Sr, Ba, Ca, Zr, Hf inside oxygen atmosphere at O2 pressure of 1×10-4 mBar or less, amorphous oxide is formed to SiO2 oxide, the substrate 10 and an SiO2 layer are exposed to Sr and oxygen beam O2 and SrO is combined with SiO2 and changes an SiO2 layer to a crystalline seed layer 20 formed of SrSiO4 or SrSiO3, etc. Then, a high dielectric oxide layer 22 is formed by supplying crystalline silicate simultaneously or alternately under the conditions of 350 to 650 deg.C and O2 partial pressure of 1×10-4 mBar or less to a surface 21 of the seed layer 20.

    DUAL WAVELENGTH MONOLITHICALLY INTEGRATED VERTICAL CAVITY SURFACE-EXITING LASERS(VCSEL) AND METHOD OF FABRICATION

    公开(公告)号:JPH1146039A

    公开(公告)日:1999-02-16

    申请号:JP6780598

    申请日:1998-03-02

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To make a low-cost semiconductor chip containing dual wavelength, monolithically integrated VCSEL, which is capable of read/write applications for both CDs and SVDs, while meeting the requirements for the interchangeability in the reverse direction. SOLUTION: This method of fabrication for exiting long and short wavelength beams, containing a first mirror stack lattice-matching with a dual wavelength monolithically integrated vartical cavity surface-exiting lasers(VCSEL) and a substrate 12 surface. Respective VCSELs contain a mirror pair of a AlAs/AlGaAs material system, an active region lattice-matches with the surface of the first mirror stack, while the second mirror stack lattice-matches with the surface of the active region, making feasible the exiting of either a short or a long wavelength beam depending on the design parameter. Moreover, the electric contact couples with the active region of the monolithically integrated short wavelength VCSEL and the monolithically integrated long wavelength VCSEL. In such a constitution, the dual wavelength monolithically integrated VCSEL is fabricated as a semiconductor laser chip which is capable of read/write applications for both CD and DVD.

    LONG-WAVELENGTH VCSEL
    14.
    发明专利

    公开(公告)号:JPH10303515A

    公开(公告)日:1998-11-13

    申请号:JP12680998

    申请日:1998-04-21

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide a long-wavelength vertical cavity surface emitting laser(VCSEL) whose reliability is high. SOLUTION: A VCSEL which emits long-wavelength light is provided with an active structure 23 sandwiched between a GaAs (111) substrate element 12, a first mirror stack 14 which is composed of a GaAs/AlGaAs substance-based mirror pair and whose latticle is made to agree with a GaInAsN active region 2, a first cladding region 24 adjacent to the first mirror stack 14 and a second cladding region 25. The active structure 23 contains a GaInAsN active region 20 containing quantum wells 35, 36, 37 using a nitride as a base, and a second mirror stack 26 whose lattice is made to agree with the second cladding region 25 and which comprises a GaAs/AlGaAs substance-based mirror pair.

    VERTICAL CAVITY FACE EMISSION LASER FOR HIGH OUTPUT OPERATION AND FABRICATION THEREOF

    公开(公告)号:JPH10256654A

    公开(公告)日:1998-09-25

    申请号:JP4620498

    申请日:1998-02-10

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide a vertical cavity face emission laser for high power operation excellent in reliability, stability and cost efficiency, and fabrication method thereof. SOLUTION: The VCSEL (vertical cavity face emission laser) for high power operation comprises a substrate 42, and a heat dissipation layer 54, a first mirror stack 26, an active region 21 having a grating aligned with that of the first mirror stack 26, and a second mirror stack 18 having a grating aligned with that of the active region 21 arranged on the substrate element 42. Electric contacts are arranged on the opposite surfaces of the active region 21. At first, the VCSEL is formed as two wafer structures 10, 40 each including a heat dissipation layer 30, 44. The two water structures 10, 40 are flip-chip mounted and fused each other to form a single heat dissipation layer 54. Subsequently, that structure is subjected to selective etching in order to remove the substrate element 42 on which the first wafer structure 10 is formed.

    VCSEL HAVING VISIBLE LIGHT DISTRIBUTED BRAGG REFLECTOR

    公开(公告)号:JPH104243A

    公开(公告)日:1998-01-06

    申请号:JP6914797

    申请日:1997-03-05

    Applicant: MOTOROLA INC

    Abstract: PROBLEM TO BE SOLVED: To provide a vertical cavity surface emitting laser having a visible light distributed Bragg reflector. SOLUTION: A first set distributed Bragg reflector 103 is deposited on the first surface of a vertical cavity surface emitting laser including a semiconductor substrate 102. The distributed Bragg reflector 103 is made of alternating layers of indium phosphide aluminum gallium and aluminum arsenide. After arranging an active region 106 on a distributed Bragg reflector, a cladding region 107 is provided following the active region 106. Another distributed Bragg reflector 103 is provided on the cladding region 107.

    Semiconductor structures and devices not lattice matched to the substrate

    公开(公告)号:AU2002309954A1

    公开(公告)日:2003-02-17

    申请号:AU2002309954

    申请日:2002-05-16

    Applicant: MOTOROLA INC

    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates (22) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer (24) comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (28) of silicon oxide. The amorphous interface layer (28) dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer (24). The accommodating buffer layer (24) is substantially lattice matched to both the underlying silicon wafer (22) and the overlying monocrystalline material layer (26). Any lattice mismatch between the accommodating buffer layer (24) and the underlying silicon substrate (22) is taken care of by the amorphous interface layer (28). In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials.

    18.
    发明专利
    未知

    公开(公告)号:DE69621719T2

    公开(公告)日:2002-10-31

    申请号:DE69621719

    申请日:1996-08-16

    Applicant: MOTOROLA INC

    Abstract: A short wavelength VCSEL including a mirror stack (10) positioned on a substrate (11), formed of a plurality of pairs of relatively high and low index of refraction layers a second mirror stack (15) formed of a plurality of pairs of relatively high and low index of refraction layers, an active region (12) sandwiched between the first stack (10) and the second stack (15), the active region (12) being formed of quantum well layers (20, 21, 22) of GaAsP having barrier layers (25, 26) of GaInP sandwiched therebetween, the quantum well (20, 21, 22) and barrier layers (25, 26) having substantially equal and opposite lattice mismatch.

    19.
    发明专利
    未知

    公开(公告)号:DE69621719D1

    公开(公告)日:2002-07-18

    申请号:DE69621719

    申请日:1996-08-16

    Applicant: MOTOROLA INC

    Abstract: A short wavelength VCSEL including a mirror stack (10) positioned on a substrate (11), formed of a plurality of pairs of relatively high and low index of refraction layers a second mirror stack (15) formed of a plurality of pairs of relatively high and low index of refraction layers, an active region (12) sandwiched between the first stack (10) and the second stack (15), the active region (12) being formed of quantum well layers (20, 21, 22) of GaAsP having barrier layers (25, 26) of GaInP sandwiched therebetween, the quantum well (20, 21, 22) and barrier layers (25, 26) having substantially equal and opposite lattice mismatch.

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