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    Thin compound semiconductor structure
    3.
    发明专利
    Thin compound semiconductor structure 未知

    公开(公告)号：AU7491301A

    公开(公告)日：2002-01-14

    申请号：AU7491301

    申请日：2001-05-21

    Applicant: MOTOROLA INC

    Inventor： FEKETE DOUGLAS D ,  OOMS WILLIAM J

    IPC: H01L21/20 ,  H01L21/316 ,  H01L21/30 ,  H01L21/31 ,  H01L21/36 ,  H01L21/46 ,  H01L21/469 ,  H01L23/10 ,  H01L23/58 ,  H01L31/0328

    Abstract: Semiconductor structures including compound semiconductor devices formed in semiconductor substrates and methods of producing the semiconductor devices and substrates that have improved thermal characteristics over conventional compound semiconductor devices and that may be formed substantially thinner than conventional semiconductor devices and substrates. The compound devices (1010) are formed in a layer of compound semiconductor material (1020) which overlies an accommodating layer (1030). The accommodating layer (1030) overlies a monocrystalline silicon semiconductor layer (1040). During the fabrication process, the silicon layer may be thinned by suitable methods, or removed entirely by chemical etching. When the silicon is removed by etching, the accommodating layer provides an etch-stop layer to protect the devices in the compound semiconductor layer.

    5.
    发明专利
    未知

    公开(公告)号：DE69226909T2

    公开(公告)日：1999-06-17

    申请号：DE69226909

    申请日：1992-06-30

    Applicant: MOTOROLA INC

    Inventor： ZHU THEODORE ,  OOMS WILLIAM J ,  ABROKWAH JONATHAN K ,  SHURBOFF CARL L ,  GORONKIN HERBERT

    IPC: H01L21/8232 ,  H01L27/06 ,  H01L27/11 ,  H03K19/08

    Abstract: Logic circuits using a heterojunction field effect transistor structure having vertically stacked complementary devices is provided. A P-channel quantum well (12) and an N-channel quantum well (14) are formed near each other under a single gate electrode (17) and separated from each other by a thin layer of barrier material (13). P-source and P-drain regions (18) couple to the P-channel. N-source and N-drain regions (19) couple to the N-channel. The P-source/drain regions (18) are electrically isolated from the N-source/drain regions (19) so the P-channel and N-channel devices may be interconnected to provide many logic functions.

    FREQUENCY SYNTHESIZER USING MULTIPLE DUAL MODULUS PRESCALERS
    6.
    发明专利
    FREQUENCY SYNTHESIZER USING MULTIPLE DUAL MODULUS PRESCALERS 未知

    公开(公告)号：CA1150371A

    公开(公告)日：1983-07-19

    申请号：CA368265

    申请日：1981-01-12

    Applicant: MOTOROLA INC

    Inventor： OOMS WILLIAM J

    IPC: H03L7/18 ,  H03K23/66 ,  H03L7/193 ,  H03L7/197 ,  H03B19/14

    Abstract: 20- An improved frequency synthesizer suitable for use in mobile and portable radio applications using multiple dual modulus prescalers to achieve high frequency operation and low current drain. A first high speed prescaler of limited size is used in conjunction with a second prescaler to avoid the use of one large high speed prescaler to attain high frequency operation. Consequently, the frequency synthesizer can be constructed using only a minimum amount of high speed, high current drain logic thereby reducing costs and power consumption.

    Quantum well infrared photodetector
    8.
    发明专利
    Quantum well infrared photodetector 未知

    公开(公告)号：AU3046002A

    公开(公告)日：2002-06-18

    申请号：AU3046002

    申请日：2001-11-19

    Applicant: MOTOROLA INC

    Inventor： FINDER JEFFREY M ,  OOMS WILLIAM J

    IPC: H01L21/20 ,  H01L21/316 ,  H01L31/0352 ,  H01L31/0368 ,  H01L31/101 ,  H01L31/00

    Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. One way to achieve the formation of a compliant substrate includes first growing an accommodating buffer layer (204) on a silicon wafer (202). The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (206) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Quantum well infrared photodetectors (200) can be grown on the high quality epitaxial monocrystalline material formed on such compliant substrates to create highly reliable devices having reduced costs.

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