公开(公告)号：US06187610B1

公开(公告)日：2001-02-13

申请号：US09113573

申请日：1998-07-10

Applicant: Gregg Joseph Armezzani ,  Robert Nicholas Ives ,  Mark Vincent Pierson ,  Terry Alan Tull

Inventor： Gregg Joseph Armezzani ,  Robert Nicholas Ives ,  Mark Vincent Pierson ,  Terry Alan Tull

IPC: H01L2144

CPC classification number: H05K1/112 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/49894 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/12044 ,  H05K1/0393 ,  H05K3/0094 ,  H05K3/3452 ,  H05K3/3457 ,  H05K3/3478 ,  H05K2201/0989 ,  H05K2201/10734 ,  H05K2203/041 ,  H05K2203/0455 ,  H05K2203/1394 ,  H05K2203/1572 ,  H01L2224/29099 ,  H01L2924/00

Abstract: An electronic package is provided that includes a flexible polyimide film carrier having electronic circuitry on both of its major surfaces and a plurality of solder interconnection pads on a first major surface; solder mask layers located on both major surfaces, provided that areas between subsequently to be applied individual circuit chips on the first major surface exist that are free from the solder mask; and a plurality of modules attached to the film carrier by the solder balls or bumps. Also provided is a method for fabricating the electronic package that includes reflow of the solder balls or bumps to achieve attachment of the modules.

Abstract translation: 提供了一种电子封装，其包括在其主要表面上具有电子电路的柔性聚酰亚胺膜载体和在第一主表面上的多个焊料互连焊盘; 焊接掩模层位于两个主表面上，只要在第一主表面上随后施加单个电路芯片之间的区域就不存在焊接掩模; 以及通过焊球或凸起附接到胶片载体的多个模块。 还提供了一种用于制造电子封装的方法，其包括焊球或凸块的回流以实现模块的附接。

公开(公告)号：US6165885A

公开(公告)日：2000-12-26

申请号：US115130

申请日：1998-07-14

Applicant: Michael Anthony Gaynes ,  Mark Vincent Pierson

Inventor： Michael Anthony Gaynes ,  Mark Vincent Pierson

IPC: B23K1/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/485 ,  H01L23/498 ,  H05K3/32 ,  H05K3/34 ,  H01L21/44

CPC classification number: H01L24/12 ,  B23K1/0016 ,  B23K2101/40 ,  H01L21/4867 ,  H01L21/563 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/11003 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/742 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K3/321 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/035 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/043 ,  H05K2203/0557 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05624 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2924/01004

Abstract: An electronic component with solder ball connections is provided. A stencil is produced with holes passing through it in an arrangement corresponding to an arrangement of conductive pads on a substrate or integrated circuit. The stencil is made of a solder reflow compatible material. A layer of adhesive is applied to the stencil which is then positioned with the layer of adhesive adjacent the substrate or integrated circuit with the holes aligned with the conductive pads. Solder paste is deposited in the holes and is heated along with the conductive pads to form solder balls on the conductive pads.

Abstract translation: 提供了具有焊球连接的电子部件。 制造出一种模板，其孔穿过其中，其布置对应于衬底或集成电路上的导电焊盘的布置。 模板由回流焊料兼容的材料制成。 将一层粘合剂施加到模板，然后将其与粘合剂层邻近基板或集成电路定位，其中孔与导电垫对准。 将焊膏沉积在孔中并与导电焊盘一起加热，以在导电焊盘上形成焊球。

公开(公告)号：US5875011A

公开(公告)日：1999-02-23

申请号：US834861

申请日：1997-04-10

Applicant: Mark Vincent Pierson ,  Michael Anthony Gaynes ,  David Brian Stone ,  Thurston Bryce Youngs

Inventor： Mark Vincent Pierson ,  Michael Anthony Gaynes ,  David Brian Stone ,  Thurston Bryce Youngs

IPC: G02F1/13 ,  G02F1/1333 ,  H05K3/34 ,  H05K3/36 ,  H05K3/40 ,  G02F1/133 ,  G02F1/1345

CPC classification number: G02F1/13452 ,  G02F1/13336 ,  H05K3/3442 ,  H05K3/368 ,  H05K3/403

Abstract: A liquid crystal display is provided wherein a plurality of liquid crystal display tiles are arranged in a matrix and are electrically interconnected to a tile carrier by depositing an electrically conductive metal on a sidewall edge of the liquid crystal display such as by plating, evaporation, or sputtering. Also provided is the method for forming the liquid crystal display.

Abstract translation: 提供了一种液晶显示器，其中多个液晶显示瓦片以矩阵形式布置并且通过在液晶显示器的侧壁边缘上沉积导电金属而电瓷互连到瓦片载体，例如通过电镀，蒸发或 溅射。 还提供了形成液晶显示器的方法。

公开(公告)号：US5777705A

公开(公告)日：1998-07-07

申请号：US865713

申请日：1997-05-30

Applicant: Mark Vincent Pierson ,  Steven F. Arndt ,  Michael Anthony Gaynes ,  Lawrence Richard Cutting ,  David Brian Stone

Inventor： Mark Vincent Pierson ,  Steven F. Arndt ,  Michael Anthony Gaynes ,  Lawrence Richard Cutting ,  David Brian Stone

IPC: G02F1/1333 ,  G02F1/1345

CPC classification number: G02F1/13336 ,  G02F1/1345 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48472 ,  H01L2924/01322

Abstract: A plurality of liquid crystal display tiles arranged in a matrix are electrically interconnected to a tile carrier by wire bonds.

Abstract translation: 以矩阵形式布置的多个液晶显示瓦片通过引线接合与瓷砖载体电互连。

公开(公告)号：US5759737A

公开(公告)日：1998-06-02

申请号：US709375

申请日：1996-09-06

Applicant: Natalie Barbara Feilchenfeld ,  Stephen Joseph Fuerniss ,  Michael Anthony Gaynes ,  Mark Vincent Pierson ,  Pat Hoontrakul

Inventor： Natalie Barbara Feilchenfeld ,  Stephen Joseph Fuerniss ,  Michael Anthony Gaynes ,  Mark Vincent Pierson ,  Pat Hoontrakul

IPC: G03F7/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/60 ,  H01L23/498 ,  H05K3/12 ,  H05K3/28 ,  H05K3/32 ,  H05K3/34 ,  G03C5/00

CPC classification number: H01L24/16 ,  G03F7/00 ,  G03F7/0035 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/4867 ,  H01L21/563 ,  H01L23/49816 ,  H01L24/12 ,  H01L24/29 ,  H01L24/83 ,  H05K3/321 ,  H05K3/3484 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/29101 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8319 ,  H01L2224/838 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K2201/0218 ,  H05K2201/0245 ,  H05K2201/10674 ,  H05K2201/10984 ,  H05K2203/0568 ,  H05K2203/0577 ,  H05K2203/0769 ,  H05K3/1216 ,  H05K3/28 ,  H05K3/3463

Abstract: Chip carrier packages, integrated circuits, wiring boards, and assemblies in computer systems are made having conductive adhesive interconnections. Electrically conductive polymer paste with metal particles and powders are used with photoimagable polymer films to form the interconnection structure. These articles are produced with screening and printing processes using a screening head and printing machine.

Abstract translation: 计算机系统中的芯片载体封装，集成电路，布线板和组件被制成具有导电粘合剂互连。 具有金属颗粒和粉末的导电聚合物浆料与光可塑聚合物膜一起使用以形成互连结构。 这些物品使用筛选头和印刷机进行筛选和印刷。

公开(公告)号：US5672980A

公开(公告)日：1997-09-30

申请号：US602167

申请日：1996-02-15

Applicant: Richard Gordon Charlton ,  George Charles Correia ,  Mark Andrew Couture ,  Gary Ray Hill ,  Kibby Barth Horsford ,  Anthony Paul Ingraham ,  Michael David Lowell ,  Voya Rista Markovich ,  Gordon Charles Osborne, Jr. ,  Mark Vincent Pierson

Inventor： Richard Gordon Charlton ,  George Charles Correia ,  Mark Andrew Couture ,  Gary Ray Hill ,  Kibby Barth Horsford ,  Anthony Paul Ingraham ,  Michael David Lowell ,  Voya Rista Markovich ,  Gordon Charles Osborne, Jr. ,  Mark Vincent Pierson

IPC: G01R1/04 ,  G01R1/073 ,  G01R31/28

CPC classification number: G01R1/0483 ,  G01R1/07307 ,  G01R31/2863 ,  G01R31/2886

Abstract: A method and apparatus for testing semi-conductor chips is disclosed. The individual semiconductor chips have I/O contacts. The apparatus is provided with an interposer that has contacts corresponding to the contacts on the semiconductor chip. Both the chip and the interposer contacts can be any known type including metal ball, bumps, or tabs or may be provided with dendritic surfaces. The chip contacts are first brought into relative loose temporary contact with the contacts on the interposer and then a compressive force greater that 5 grams per chip contact is applied to the chip to force the chip contacts into good electrical contact with the interposer contacts. Testing of the chip is then performed. The tests may include heating of the chip as well as the application of signals to the chip contacts. After testing the chip is removed from the substrate.

Abstract translation: 公开了一种用于测试半导体芯片的方法和装置。 单个半导体芯片具有I / O触点。 该装置设置有具有对应于半导体芯片上的触点的触点的插入器。 芯片和内插器触点都可以是任何已知的类型，包括金属球，凸块或凸片，或者可以设置有树枝状表面。 首先将芯片触点与插入件上的触点进行相对松动的临时接触，然后将大于每芯片接触5克的压缩力施加到芯片上以迫使芯片触头与插入器触点良好地电接触。 然后进行芯片的测试。 测试可能包括加热芯片以及将信号应用于芯片触点。 测试后，芯片从基板上取下。

公开(公告)号：US06759738B1

公开(公告)日：2004-07-06

申请号：US09250524

申请日：1999-02-16

Applicant: Kenneth Michael Fallon ,  Christian Robert Le Coz ,  Mark Vincent Pierson

Inventor： Kenneth Michael Fallon ,  Christian Robert Le Coz ,  Mark Vincent Pierson

IPC: H01L2348

CPC classification number: H01L24/12 ,  B23K1/0016 ,  B23K2101/40 ,  H01L21/4867 ,  H01L21/563 ,  H01L23/49805 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05184 ,  H01L2224/05572 ,  H01L2224/11003 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1182 ,  H01L2224/1184 ,  H01L2224/13006 ,  H01L2224/13011 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/742 ,  H01L2224/81136 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15321 ,  H01L2924/15787 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3511 ,  H01L2924/3841 ,  H05K3/321 ,  H05K3/3436 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/035 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/043 ,  H05K2203/0557 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05624 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2924/01004

Abstract: A substrate is provided with vias communicating with surface contacts or bumps. Joining material paste is forced through holes in a screen onto an area array of the contacts on the substrate then the screen is biased against the substrate as the paste is heated and cooled to transfer the joining material onto the contacts. Alternately, joining material paste is forced into the screen and then a substrate is placed onto the screen with an area array of bump contacts of the substrate in contact with the solder paste, and then the paste is heated and cooled to transfer the material onto the bumps. The joining material may be a solder paste, conductive adhesive paste, or transient liquid bond paste. The substrate may be a semiconductor chip substrate, flexible or rigid organic substrate, or a metal substrate coated to form a dielectric surface. Also, the substrate may be a computer chip, chip carrier substrate or a circuit board substrate. The process may be used to produce flip chips, ball grid array modules, column grid array modules, circuit boards, and attachment structures of the preceding components including information handling systems.

Abstract translation: 衬底设置有与表面接触或凸起连通的通孔。 连接材料糊料被迫通过筛网上的孔到基板上的触点的区域阵列上，然后当膏被加热和冷却以将接合材料转移到触点上时，屏幕被偏压到基板上。 或者，将接合材料糊剂强制进入筛网，然后将基板放置在具有与焊膏接触的基板的凸起接触的区域阵列的屏幕上，然后将该浆料加热并冷却以将材料转移到 颠簸 接合材料可以是焊膏，导电粘合剂糊或瞬态液体粘合膏。 衬底可以是半导体芯片衬底，柔性或刚性有机衬底或涂覆以形成电介质表面的金属衬底。 此外，基板可以是计算机芯片，芯片载体基板或电路板基板。 该过程可用于制造包括信息处理系统的前述组件的倒装芯片，球栅阵列模块，列网格阵列模块，电路板和附接结构。

公开(公告)号：US06492724B2

公开(公告)日：2002-12-10

申请号：US09798829

申请日：2001-03-02

Applicant: Michael Anthony Gaynes ,  Mark Vincent Pierson ,  Aleksander Zubelewicz

Inventor： Michael Anthony Gaynes ,  Mark Vincent Pierson ,  Aleksander Zubelewicz

IPC: H01L2334

CPC classification number: H01L23/3135 ,  H01L21/563 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/12044 ,  H01L2924/15311 ,  H01L2924/00

Abstract: A structure and methods for reinforcing a semiconductor device to prevent cracking is provided. The device may take the form of a semiconductor chip or a semiconductor chip package. When a semiconductor chip is provided, an adhesion layer is applied over its top surface, followed by the application of a reinforcing layer over the adhesion layer. When a semiconductor chip package is provided, the package first undergoes a cleaning process, followed by the application of an adhesion layer over its top surface and, lastly, the application of a reinforcing layer over the adhesion layer.

Abstract translation: 提供了用于加强半导体器件以防止开裂的结构和方法。 该器件可以采取半导体芯片或半导体芯片封装的形式。 当提供半导体芯片时，在其顶表面上施加粘合层，随后在粘合层上施加增强层。 当提供半导体芯片封装时，封装首先进行清洁处理，然后在其顶表面上施加粘合层，最后在粘合层上施加增强层。

公开(公告)号：US06399892B1

公开(公告)日：2002-06-04

申请号：US09665365

申请日：2000-09-19

Applicant: Cynthia Susan Milkovich ,  Mark Vincent Pierson ,  Charles Gerard Woychik

Inventor： Cynthia Susan Milkovich ,  Mark Vincent Pierson ,  Charles Gerard Woychik

IPC: H05K100

CPC classification number: H05K3/4688 ,  H01L23/3735 ,  H01L23/49827 ,  H01L2224/05023 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/09701 ,  H05K1/0271 ,  H05K1/036 ,  H05K1/113 ,  H05K1/141 ,  H05K3/429 ,  H05K3/4641 ,  H05K2201/0133 ,  H05K2201/068 ,  H05K2201/10378 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. A second dielectric layer, on the laminate chip carrier side of the interposer, is made of resilient, low elastic modulus, material with metallurgy formed thereon, such as circuit board material, with a composite CTE closely matching the CTE of said chip carrier. A third dielectric intermediate layer, laminated between said first and second layers, is made of a low elastic modulus material with metallurgy formed thereon, such as a Teflon/glass particle material, with a composite CTE between the CTEs of said first and second layers.

Abstract translation: 一种用于将半导体芯片连接到层压芯片载体的多层CTE补偿芯片插入器。 在插入器的芯片侧上的第一电介质层由硬度高的弹性模量的材料制成，例如陶瓷材料，CTE与芯片的CTE密切匹配。 中间层的层叠芯片载体侧上的第二介电层由弹性低弹性模量制成，其上形成有诸如电路板材料之间的冶金材料，具有与所述芯片载体的CTE密切匹配的复合CTE。 层压在所述第一和第二层之间的第三介电中间层由其上形成有冶金的低弹性模量材料制成，例如特氟隆/玻璃颗粒材料，在所述第一和第二层的CTE之间具有复合CTE。

公开(公告)号：US6018866A

公开(公告)日：2000-02-01

申请号：US23552

申请日：1998-02-13

Applicant: Alan Harris Crudo ,  John Gillette Davis ,  Christian Robert Le Coz ,  Mark Vincent Pierson ,  Amit Kumar Sarkhel ,  Ajit Kumar Trivedi

Inventor： Alan Harris Crudo ,  John Gillette Davis ,  Christian Robert Le Coz ,  Mark Vincent Pierson ,  Amit Kumar Sarkhel ,  Ajit Kumar Trivedi

IPC: H01L23/12 ,  H05K3/00 ,  H05K3/22 ,  H05K3/34 ,  H05K3/42 ,  H05K3/46 ,  B23P19/00

CPC classification number: H05K3/3436 ,  H05K3/225 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K2201/0949 ,  H05K2201/10287 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/175 ,  H05K3/0047 ,  H05K3/341 ,  H05K3/429 ,  Y02P70/613 ,  Y10T29/49124 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49153 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49723 ,  Y10T29/49726 ,  Y10T29/49728 ,  Y10T29/4973 ,  Y10T29/49734 ,  Y10T29/49815 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53274

Abstract: A method and apparatus for efficiently repairing or reworking a printed circuit board having a solder ball grid array thereon efficiently and at minimum cost includes the steps of drilling out a plated-through hole to sever electrical connections between a ball grid array pad on one surface of the printed circuit board and internal circuits and circuits on an opposite surface of the printed circuit board; inserting a pin having an insulated sleeve surrounding a portion thereof into the drilled-out hole, the pin having attached to one end a wire for attachment to the ball grid array on one surface of the printed circuit board and a post at the other end of the pin for attachment of a wire to the post; the pin having a stop along its length to control vertical positioning of the pin in the drilled-out hole, the pin referred to as a via replacement (VR) pin. Alternately, after the plated through hole is drilled out, an insulated wire may be inserted into the hole with insulation removed from the length of the wire which extends beyond one surface of the printed circuit board. The bare length of wire is bent parallel to the surface of the printed circuit board and attached thereto by a solder reflow process. In a dog bone configuration, the wire is formed around a pad on the surface of the printed circuit board which receives the solder ball.