Microelectronics H-frame device
    14.
    发明授权

    公开(公告)号:US12122666B2

    公开(公告)日:2024-10-22

    申请号:US17198700

    申请日:2021-03-11

    Abstract: A microelectronics H-frame device includes: a stack of two or more substrates wherein the substrate stack comprises a top substrate and a bottom substrate, wherein bonding of the top substrate to the bottom substrate creates a vertical electrical connection between the top substrate and the bottom substrate, wherein the top surface of the top substrate comprises top substrate top metallization, wherein the bottom surface of the bottom substrate comprises bottom substrate bottom metallization; mid-substrate metallization located between the top substrate and the bottom substrate; a micro-machined top cover bonded to a top side of the substrate stack; and a micro-machined bottom cover bonded to a bottom side of the substrate stack.

    Channelized filter using semiconductor fabrication

    公开(公告)号:US11658136B2

    公开(公告)日:2023-05-23

    申请号:US17745265

    申请日:2022-05-16

    CPC classification number: H01L23/66 H01P1/20327 H01L2223/6627 H01L2223/6655

    Abstract: A semiconductor technology implemented high-frequency channelized filter includes a dielectric substrate with metal traces disposed on one of two major surfaces of the substrate. An input and output port disposed on the substrate and one of the metal traces carrying a high-frequency signal to be filtered between the input and output port. Other of the metal traces are connected to the one metal trace at intervals along the length of the one metal trace each providing a reactance to the high-frequency signal where the reactance varies with frequency and additional traces of the metal traces serving as a reference ground for the one metal trace and the other metal traces. A silicon enclosure mounted to the substrate with a first planar surface with cavities in the enclosure that extend through the first surface, and internal walls within the silicon enclosure defining the cavities. A layer of conductive metal covers the first planar surface, cavities and the internal walls. The silicon enclosure having substantially continuous areas of metal on the first planar surface about the periphery of the silicon enclosure that engage corresponding areas of the additional traces about the periphery of the substrate. The cavities surround the respective other metal traces with the internal cavity walls engaging the additional traces adjacent the respective other metal traces to individually surround each of the other metal traces with a conductive metal thereby providing electromagnetic field isolation between each of the other metal traces.

    Channelized filter using semiconductor fabrication

    公开(公告)号:US11837561B2

    公开(公告)日:2023-12-05

    申请号:US18123467

    申请日:2023-03-20

    CPC classification number: H01L23/66 H01P1/20327 H01L2223/6627 H01L2223/6655

    Abstract: A semiconductor technology implemented high-frequency channelized filter includes a dielectric substrate with metal traces disposed on one of two major surfaces of the substrate. An input and output port disposed on the substrate and one of the metal traces carrying a high-frequency signal to be filtered between the input and output port. Other of the metal traces are connected to the one metal trace at intervals along the length of the one metal trace each providing a reactance to the high-frequency signal where the reactance varies with frequency and additional traces of the metal traces serving as a reference ground for the one metal trace and the other metal traces. A silicon enclosure mounted to the substrate with a first planar surface with cavities in the enclosure that extend through the first surface, and internal walls within the silicon enclosure defining the cavities. A layer of conductive metal covers the first planar surface, cavities and the internal walls. The silicon enclosure having substantially continuous areas of metal on the first planar surface about the periphery of the silicon enclosure that engage corresponding areas of the additional traces about the periphery of the substrate. The cavities surround the respective other metal traces with the internal cavity walls engaging the additional traces adjacent the respective other metal traces to individually surround each of the other metal traces with a conductive metal thereby providing electromagnetic field isolation between each of the other metal traces.

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