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    14.
    发明专利
    未知

    公开(公告)号：SE0850083L

    公开(公告)日：2010-05-20

    申请号：SE0850083

    申请日：2008-11-19

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： EBEFORS THORBJOERN ,  KAELVESTEN EDVARD ,  BAUER TOMAS

    Abstract: A wafer level method of making a micro-electronic and/or micro-mechanic device, having a capping with electrical wafer through connections (vias), comprising the steps of providing a first wafer of a semiconductor material having a first and a second side and a plurality of holes and/or recesses in the first side, and a barrier structure extending over the wafer on the second side, said barrier comprising an inner layer an insulating material, such as oxide, and an outer layer of another material. Then, metal is applied in said holes so as to cover the walls in the holes and the bottom of the holes. The barrier structure is removed and contacts are provided to the wafer through connections on the back-side of the wafer. Bonding structures are provided on either of said first side or the second side of the wafer. The wafer is bonded to another wafer carrying electronic and micro-electronic/mechanic components, such that the first wafer forms a capping structure covering the second wafer. Finally the wafer is singulated to individual devices.

    DEFLECTABLE MICROSTRUCTURE AND METHOD OF MANUFACTURING THE SAME THROUGH BONDING OF WAFERS
    16.
    发明专利
    DEFLECTABLE MICROSTRUCTURE AND METHOD OF MANUFACTURING THE SAME THROUGH BONDING OF WAFERS 未知

    公开(公告)号：CA2473836A1

    公开(公告)日：2003-08-21

    申请号：CA2473836

    申请日：2003-02-14

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： SVEDIN NIKLAS ,  EBEFORS THORBJOERN ,  WESTIN HAEKAN ,  KAELVESTEN EDVARD

    IPC: B81B3/00 ,  B81B7/04 ,  G02F1/29 ,  H01L21/00 ,  H01L21/30 ,  H01L21/302 ,  H01L21/46 ,  H01L21/461

    Abstract: The invention relates to a method of making a deflectable, free hanging micr o structure comprising at least one hinge member, the method comprising the steps of providing a first sacrificial wafer comprising a single crystalline material constituting material forming the micro structure. A second semiconductor wafer comprising necessary components for forming the structur e in cooperation with said first wafer is provided. Finite areas of a structur ed bonding material is provided, on one or both of said wafers at selected locations, said finite areas defining points of connection for joining said wafers. The wafers are bonded using heat and optionally pressure. Sacrificia l material is etched away from said sacrificial wafer, patterning the top wafe r by lithography is performed to define the desired deflectable microstructure s having hinges, and subsequently silicon etch to make the structures.

    20.
    发明专利
    未知

    公开(公告)号：SE0801620L

    公开(公告)日：2008-10-30

    申请号：SE0801620

    申请日：2007-01-31

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： KAELVESTEN EDVARD ,  BAUER TOMAS ,  EBEFORS THORBJOERN

    Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

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