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    DEFLECTABLE MICROSTRUCTURE AND METHOD OF MANUFACTURING THE SAME THROUGH BONDING OF WAFERS
    12.
    发明专利
    DEFLECTABLE MICROSTRUCTURE AND METHOD OF MANUFACTURING THE SAME THROUGH BONDING OF WAFERS 未知

    公开(公告)号：CA2473836A1

    公开(公告)日：2003-08-21

    申请号：CA2473836

    申请日：2003-02-14

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： SVEDIN NIKLAS ,  EBEFORS THORBJOERN ,  WESTIN HAEKAN ,  KAELVESTEN EDVARD

    IPC: B81B3/00 ,  B81B7/04 ,  G02F1/29 ,  H01L21/00 ,  H01L21/30 ,  H01L21/302 ,  H01L21/46 ,  H01L21/461

    Abstract: The invention relates to a method of making a deflectable, free hanging micr o structure comprising at least one hinge member, the method comprising the steps of providing a first sacrificial wafer comprising a single crystalline material constituting material forming the micro structure. A second semiconductor wafer comprising necessary components for forming the structur e in cooperation with said first wafer is provided. Finite areas of a structur ed bonding material is provided, on one or both of said wafers at selected locations, said finite areas defining points of connection for joining said wafers. The wafers are bonded using heat and optionally pressure. Sacrificia l material is etched away from said sacrificial wafer, patterning the top wafe r by lithography is performed to define the desired deflectable microstructure s having hinges, and subsequently silicon etch to make the structures.

    ELECTRICAL CONNECTIONS IN SUBSTRATES
    13.
    发明专利
    ELECTRICAL CONNECTIONS IN SUBSTRATES 未知

    公开(公告)号：CA2519893C

    公开(公告)日：2013-03-12

    申请号：CA2519893

    申请日：2004-03-22

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： KAELVESTEN EDVARD ,  EBEFORS THORBJOERN ,  SVEDIN NIKLAS ,  RANGSTEN PELLE ,  SCHOENBERG TOMMY

    IPC: H01L21/60 ,  B81B7/00 ,  H01L21/768 ,  H01L23/48 ,  H01L29/40

    Abstract: The invention relates to a method of making an electrical connection between a first (top) and a second (bottom) surface of a conducting or semi-conducting substrate. It comprising creating a trench in the first surface, and establishing an insulating enclosure entirely separating a portion of said substrate, defined by said trench. It also relates to a product usable as a starting substrate for the manufacture of micro-electronic and/or micro-mechanic devices, comprising a flat substrate of a semi-conducting or conducting material, and having a first and a second surface and at least one electrically conducting member extending through said substrate. The electrically conducting member is insulated from surrounding material of the flat substrate by a finite layer of an insulating material, and comprises the same material as the substrate, i.e. it is made from the wafer material.

    15.
    发明专利
    未知

    公开(公告)号：AT511703T

    公开(公告)日：2011-06-15

    申请号：AT07709445

    申请日：2007-01-31

    Applicant: SILEX MICROSYSTEMS AB

    Inventor： KAELVESTEN EDVARD ,  BAUER TOMAS ,  EBEFORS THORBJOERN

    IPC: H01L21/768 ,  H01L23/48 ,  H01L23/522

    Abstract: The invention relates to a method of making a starting substrate wafer for semiconductor engineering having electrical wafer through connections (140; 192). It comprises providing a wafer (110; 150) having a front side and a back side and having a base of low resistivity silicon and a layer of high resistivity material on the front side. On the wafer there are islands of low resistivity material in the layer of high resistivity material. The islands are in contact with the silicon base material. Trenches are etched from the back side of the wafer but not all the way through the wafer to provide insulating enclosures defining the wafer through connections (140; 192). The trenches are filled with insulating material. Then the front side of the wafer is grinded to expose the insulating material to create the wafer through connections. Also there is provided a wafer substrate for making integrated electronic circuits and/or components, comprising a low resistivity silicon base (110) having a high resistivity top layer (122) suitable for semiconductor engineering, characterized by having low resistivity wafer through connections (140).

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