公开(公告)号：JP2003200394A

公开(公告)日：2003-07-15

申请号：JP2001394880

申请日：2001-12-26

Applicant: SONY CORP

Inventor： IKEDA KOICHI

IPC: G02B26/02 ,  B81B3/00 ,  B81C1/00 ,  G02B5/18 ,  G02B26/08

Abstract: PROBLEM TO BE SOLVED: To flatten a surface of a drive side electrode of an electrostatic drive type MEMS element. SOLUTION: A substrate side electrode 33 and a beam 35 disposed opposite to the substrate side electrode 33 and having a drive side electrode 38 driven with an electrostatic attraction or an electrostatic repulsion acting from the substrate side electrode 33 are provided. The substrate side electrode 33 is made of a conductive semiconductor region with impurities introduced thereinto in a semiconductor substrate 32. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2003175500A

公开(公告)日：2003-06-24

申请号：JP2001377653

申请日：2001-12-11

Applicant: SONY CORP

Inventor： YAMAGUCHI SEIYA ,  FUKUI TATSUO ,  IKEDA KOICHI

IPC: G02B5/18 ,  B81C3/00 ,  H01L23/02 ,  H01L27/14

Abstract: PROBLEM TO BE SOLVED: To join a substrate for forming a functional portion of a micro-device with a lid member comprising a glass plate or the like, while omitting a package material made of a ceramic or a resin, and to prevent defective airtightness caused by a crack, a crazing or the like resulting from differential thermal expansion between the substrate and the lid member, in micro-package structure. SOLUTION: The functional portion 2 of the micro-device is airtightly sealed in this micro-package structure 1A, by joining the substrate (Si substrate 3) formed with the functional portion 2 of the micro-device to the lid member (glass plate 6) provided with a spatial distance on the functional portion 2 of the micro-device with a soldering layer 9 via respective adhesive layers 7, 8. At least one out of a pattern of the adhesive layer 7 in the substrate side and a pattern of the adhesive layer 8 in the lid side is formed of a band-like pattern of which the longitudinal length is equal to a lateral length thereof in edge side length. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2001044191A

公开(公告)日：2001-02-16

申请号：JP21150199

申请日：1999-07-27

Applicant: SONY CORP

Inventor： IKEDA KOICHI ,  FUKAZAWA MASANAGA ,  KITO HIDEYOSHI ,  HASEGAWA TOSHIAKI

IPC: H01L21/302 ,  C08J7/00 ,  C08J7/04 ,  C08K3/04 ,  C08L83/04 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device, such as signal propagation delay, by reducing capacitance between interconnect layers and capacitance between interconnects while forming a silicon oxide film containing carbon on an organic insulating film. SOLUTION: A silicon oxide film 12 containing carbon is formed on an organic insulating film 11. Due to carbon present therein, the film 12 exhibits low relative permittivity while still holding the inorganic properties of a conventional silicon oxide film not containing an impurity such as carbon. Therefore, even when the insulating film having inorganic properties is formed on the film 11 having a low relative permittivity, lower relative permittivity can be achieved. Thus, a laminated insulating film 13 is interposed between interconnect layers and between interconnects, whereby capacitance between the interconnect layers and between the interconnects can be reduced, and this contributes to improving the performance of a semiconductor device, such as signal propagation delay.

公开(公告)号：JP2000150646A

公开(公告)日：2000-05-30

申请号：JP32011498

申请日：1998-11-11

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  IKEDA KOICHI

IPC: H01L21/768 ,  H01L21/283 ,  H01L21/31 ,  H01L21/312 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To prevent production of faulty embedding even when a metal film or the like is embedded in a connecting hole, by providing an anti-degassing insulating film for interrupting degassing from an organic insulating film on the inner wall of the connecting hole which is formed in an interlayer insulating film having at least an organic insulating film. SOLUTION: An organic insulating film 2 is formed in such a way that it covers wiring 1. An inorganic insulating film 3 is formed on the organic insulating film 2. In this way, an interlayer insulating film 4 comprises the organic insulating film 2 and the inorganic insulating film 3. Then a connecting hole is formed in the interlayer insulating film 4 reaching the wiring 1. Also, an anti-degassing insulating film 6 for interrupting the discharge of gas from the organic insulating film 2 is formed on the inner wall of the connecting hole 5. Further, a plug 7 is formed by embedding metal inside the connecting hole 5 and is connected to the wiring 1. Accordingly, since gas discharged from the organic insulating film 2 toward the connecting hole 5 can be blocked by the anti-degassing insulating film 6, no faulty embedding is caused.

公开(公告)号：JP2011258654A

公开(公告)日：2011-12-22

申请号：JP2010130266

申请日：2010-06-07

Applicant: Sony Corp ,  ソニー株式会社

Inventor： AKIBA AKIRA ,  MORITA SHINYA ,  IKEDA KOICHI ,  MITARAI TAKASHI

IPC: H01L23/12 ,  H01L23/14 ,  H01L25/00

CPC classification number: H01L2223/6677 ,  H01L2224/16225 ,  H01L2924/1461 ,  H01L2924/1515 ,  H01L2924/15159 ,  H01L2924/157 ,  H01L2924/19107 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an interposer which exhibits excellent high frequency characteristics while simplifying the manufacturing process.SOLUTION: A through electrode 12 is provided through a substrate 11, a dielectric layer 14A is formed on the substrate 11 and then interconnections 16A and 16B and an antenna 17 are formed on the dielectric layer 14A. Subsequently, dielectric layers 14 and 14C are laminated, respectively, on the undersurface of the substrate 11 and on the dielectric layer 14A, and a recess 19A is provided in the substrate 11 thus completing an interposer 10A. After bonding a semiconductor chip 20 to the top face side of the substrate 11, the undersurface side of the substrate 11 is mounted on a printed board 30. Since the interconnections 16A and 16B for connecting the semiconductor chip 20 and the printed board 30 are provided on the substrate 11, the manufacturing process is simplified.

Abstract translation: 要解决的问题：提供一种显示出优异的高频特性同时简化制造过程的中介层。 解决方案：通过基板11设置贯通电极12，在基板11上形成电介质层14A，然后在电介质层14A上形成布线16A，16B和天线17。 随后，电介质层14和14C分别层叠在基板11的下表面和电介质层14A上，并且在基板11中设置凹部19A，从而完成插入件10A。 在将半导体芯片20接合到基板11的顶面侧之后，将基板11的下表面侧安装在印刷电路板30上。由于设置用于连接半导体芯片20和印刷电路板30的互连16A和16B 在基板11上，简化了制造工艺。 版权所有（C）2012，JPO＆INPIT

公开(公告)号：JP2007134453A

公开(公告)日：2007-05-31

申请号：JP2005325009

申请日：2005-11-09

Applicant: Sony Corp ,  ソニー株式会社

Inventor： MITARAI TAKASHI ,  IKEDA KOICHI

IPC: H01L23/14 ,  B81B3/00 ,  B81B7/02 ,  B81C1/00

Abstract: PROBLEM TO BE SOLVED: To form a cavity wherein a micro machine surely operates, without damaging the reliability of an electronic circuit.
SOLUTION: A micro machine operation structure 7 is arranged in an opening 12a for etching which is formed in a wiring interlayer insulating layer 9, and an etching stop layer 4 is arranged under the micro machine operation structure 7. An etching protection wall 12 is formed on the inside wall surface of the opening 12a in the wiring interlayer insulating layer 9 at a necessary clearance with the micro machine operation structure 7, and a cavity 13 is formed in the arrangement portion of the micro machine operation structure 7 so as to keep its entire outer surface not being in contact with the other part. Thus, the deterioration of characteristic in an adjacent wiring due to the formation of the cavity 13 is avoided by the etching protection wall 12.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：形成微型机器可靠地工作的腔体，而不损害电子电路的可靠性。 解决方案：微机操作结构7设置在形成在布线层间绝缘层9中的用于蚀刻的开口12a中，并且在微机操作结构7下方布置有蚀刻停止层4.蚀刻保护壁 12以与微机操作结构7必需的间隙形成在布线层间绝缘层9中的开口12a的内壁面上，并且在微机操作结构7的配置部分中形成空腔13，以便 以保持其整个外表面不与另一部分接触。 因此，通过蚀刻保护壁12避免了由于形成空腔13而在相邻布线中的特性劣化。版权所有：（C）2007，JPO＆INPIT

公开(公告)号：JP2003340795A

公开(公告)日：2003-12-02

申请号：JP2002144981

申请日：2002-05-20

Applicant: Sony Corp ,  ソニー株式会社

Inventor： IKEDA KOICHI ,  KINOSHITA TAKASHI

IPC: G02B26/08 ,  B81B3/00 ,  B81C1/00 ,  G02B27/18 ,  H01S3/10 ,  H01S3/101 ,  H02N1/00

CPC classification number: B81C1/00666 ,  B81B2201/047 ,  B81B2203/053 ,  B81C2201/0169

Abstract: PROBLEM TO BE SOLVED: To flatten a beam composing an electrostatic drive type MEMS element or stabilize and uniformalize a beam shape. SOLUTION: The electrostatic drive type MEMS element comprises a substrate side electrode 33, a beam 36 disposed opposite to the substrate side electrode 33, having a drive side electrode 37 and supported on the both ends thereof, and at least two supporting parts 35A, 35B and 35C, 35D are provided on the both ends of the beam 36 respectively. In the supporting parts 35, the height t1 of the inner supporting parts 35B, 35C is set to be lower than the height t2 of the outer supporting parts 35A, 35D. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：使构成静电驱动型MEMS元件的光束变平或稳定并均匀化光束形状。 解决方案：静电驱动型MEMS元件包括基板侧电极33，与基板侧电极33相对设置的光束36，具有驱动侧电极37并被支撑在其两端，以及至少两个支撑部 35A，35B和35C，35D分别设置在梁36的两端。 在支撑部35中，内侧支撑部35B，35C的高度t1被设定为低于外部支撑部35A，35D的高度t2。 版权所有（C）2004，JPO

公开(公告)号：JP2003021794A

公开(公告)日：2003-01-24

申请号：JP2001206453

申请日：2001-07-06

Applicant: Sony Corp ,  ソニー株式会社

Inventor： IKEDA KOICHI ,  FUKUI TATSUO

IPC: G02B26/08 ,  G02B27/18

CPC classification number: G02B26/0808

Abstract: PROBLEM TO BE SOLVED: To provide an optical modulation element having a light reflection film-cum-membrane side electrode with a uniform film thickness and high light reflectance.
SOLUTION: The optical modulation element 30 is constituted as an optical modulation element which constitutes a GLV device and has the same structure as a conventional optical modulation element excluding the different structure of the light reflection film-cum-the membrane side electrode 34 of a membrane 32. The light reflection film-cum-membrane side electrode is composed of two- layer metal film of a TiN film 36 provided as a lower layer and having a film thickness of 10 nm to 70 nm and an Al film 38 provided thereon and having a film thickness of 50 nm to 150 nm. The optical modulation element has high light use efficiency because the light reflection film-cum-membrane side electrode has a flat and smooth reflective surface of the Al film 38 and exhibits high light reflectance.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：提供具有均匀膜厚和高反射率的光反射膜 - 暨膜侧电极的光调制元件。 解决方案：光调制元件30构成为构成GLV器件的光调制元件，并且具有与常规光调制元件相同的结构，不同于膜的反射膜与膜侧电极34的不同结构 光反射膜暨膜侧电极由设置为下层并具有10nm至70nm的膜厚度和设置在其上的Al膜38的TiN膜36的两层金属膜构成，并具有 膜厚度为50nm至150nm。 光调制元件由于光反射膜暨膜侧电极具有Al膜38的平坦且平滑的反射表面并且具有高的光反射率，所以具有高的光使用效率。

公开(公告)号：JP2001144086A

公开(公告)日：2001-05-25

申请号：JP2000233954

申请日：2000-08-02

Applicant: SONY CORP ,  KOBE STEEL LTD

Inventor： NOGAMI TAKESHI ,  KOMAI HISANORI ,  IKEDA KOICHI ,  KINOSHITA TAKASHI ,  SUZUKI KOHEI ,  KAWAKAMI NOBUYUKI ,  FUKUMOTO YOSHITO

IPC: H01L21/283 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a buried interconnection which has a high reliability and causes no damage or disconnections in interconnections and also causes no damage in an insulation film for filling a space between the interconnections and can have the space between the interconnections surely filled by an insulation material. SOLUTION: A method of forming a buried interconnection comprises a process (A) of forming, on a substrate 11, interconnections 33 and a first insulation film 34 for filling a space between the interconnections, a process (B) of dissolving the first insulation film 34 into a fluid 41, a process (C) of replacing the fluid 41 with a material solution 43 including a material for forming a second insulation film without bringing the interconnections 33 into contact with the air, and a process (D) of drying the material solution after filling at least the space between the interconnections 33 with the second insulation film 44 gelled in the material solution, thereby forming a second insulation film 35 at least between the interconnections 33.

公开(公告)号：JP2000323479A

公开(公告)日：2000-11-24

申请号：JP13353399

申请日：1999-05-14

Applicant: SONY CORP

Inventor： HASEGAWA TOSHIAKI ,  TAGUCHI MITSURU ,  MIYATA KOJI ,  IKEDA KOICHI

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To prevent migration of copper in a copper wiring from an interface between a barrier metal layer and a nitride layer to an interlayer insulating film and thus to prevent the occurrence of a leak current and a short circuit between neighboring wirings, by simply covering the upper surface of the copper wiring formed in a wiring trench via a barrier metal layer with a nitride film. SOLUTION: A semiconductor device having a wiring 24 formed in a recessed portion (wiring trench) 22 formed in an interlayer insulating film 21 has a first barrier layer 23 covering the wiring 24 from under the wiring 24, and a second barrier layer 25 covering the wiring 24 from over the wiring 24, wherein the first barrier layer 23 overlaps the second barrier layer 25.