公开(公告)号：JP2013026265A

公开(公告)日：2013-02-04

申请号：JP2011156533

申请日：2011-07-15

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KUBOI NOBUYUKI ,  FUKAZAWA MASANAGA

IPC: H01L21/3065 ,  H01L21/304 ,  H01L21/336 ,  H01L27/146 ,  H01L29/78

CPC classification number: H01J37/32082

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor substrate treating method which can reduce crystal defects and metal contamination, and also provide an apparatus for the method and a method of manufacturing a semiconductor device using the same.SOLUTION: A plasma treatment method includes: creating plasma from a mixed gas containing carbon and nitrogen to generate CN active species, and treating a surface of a semiconductor layer of a semiconductor substrate 11 with the generated CN active species. In particular, the treatment includes passivating the surface of the semiconductor layer of the semiconductor substrate 11 by the CN active species, thereby removing defects in a surface contaminated metal and a semiconductor.

Abstract translation: 要解决的问题：提供一种可以减少晶体缺陷和金属污染的半导体衬底处理方法，并且还提供一种用于该方法的装置和使用其的半导体器件的制造方法。 解决方案：等离子体处理方法包括：从含有碳和氮的混合气体产生等离子体以产生CN活性物质，并用所产生的CN活性物质处理半导体衬底11的半导体层的表面。 特别地，处理包括通过CN活性物质钝化半导体衬底11的半导体层的表面，从而去除表面污染的金属和半导体中的缺陷。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JPH11194499A

公开(公告)日：1999-07-21

申请号：JP156298

申请日：1998-01-07

Applicant: SONY CORP

Inventor： FUKAZAWA MASANAGA ,  KADOMURA SHINGO

IPC: G03F7/11 ,  G03F7/40 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065

Abstract: PROBLEM TO BE SOLVED: To make it possible to control the size conversion errors of the pattern size of a resist film and the patterned size of an insulating film by using an primer coating antireflection film. SOLUTION: The antireflection film 21a contg. a fluorine-contg. org. compd. is formed on the upper layer of the insulating film 20 formed on a substrate 10 and the resist film R is formed along the prescribed patterns on the upper layer of the antireflection film 21a. Next, the antireflection film 21a is etched with the resist film R as a mask while the active species of the fluorine or fluorocarbon are released from the antireflection film 21a. The insulating film 20 is then etched with the resist film R as a mask.

公开(公告)号：JPH1167909A

公开(公告)日：1999-03-09

申请号：JP22940397

申请日：1997-08-26

Applicant: SONY CORP

Inventor： FUKAZAWA MASANAGA ,  KADOMURA SHINGO

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device, with which the defective etching of an inter-layer film can be prevented when an organic low dielectric constant film is used as an inter-layer film. SOLUTION: An inter-layer film, containing at least an organic low dielectric constant film 12 above a semiconductor substrate, is formed in this semiconductor device manufacturing method. This organic low dielectric constant film is etched immediately prior to the end point of etching using O2 gas, and the remaining part of the low dielectric constant film is overetched using a forming gas. As a result, at least a part of the via hole can be formed on the organic low dielectric constant film 12. Accordingly, the defective etching of bowing shape, etc., can be prevented on the organic low dielectric constant film 12.

公开(公告)号：JP2013080813A

公开(公告)日：2013-05-02

申请号：JP2011219843

申请日：2011-10-04

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUKAZAWA MASANAGA

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/528 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/32 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/14636 ,  H01L2224/32145 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device having a connection hole in which conductive layers lying at different depths are exposed, which prevents excessive etching on the shallow conductive layer to increase yield of the semiconductor device.SOLUTION: A semiconductor device manufacturing method comprises: forming on a substrate having a first conductive layer and a second conductive layer positioned deeper than the first conductive layer inside, a large-diameter resist pattern having an opening for exposing upper parts of the first conductive layer and the second conductive layer; forming on the substrate, a large-diameter recess in which the first conductive layer is exposed on a bottom by etching by use of the large-diameter resist pattern as a mask; forming on the substrate in a formation range of the large-diameter recess, a small-diameter resist pattern having an opening for exposing the upper part of the second conductive layer; and forming on the substrate, a small-diameter recess in which the second conductive layer is exposed on a bottom by etching by use of the small-diameter resist pattern as a mask.

Abstract translation: 解决的问题：提供一种半导体器件，其具有露出不同深度的导电层的连接孔，防止对浅导电层的过度蚀刻，从而提高半导体器件的产量。 解决方案：半导体器件制造方法包括：在具有第一导电层和位于第三导电层的第二导电层的第二导电层的衬底上形成具有用于暴露上述第一导电层的上部的开口的大直径抗蚀剂图案 第一导电层和第二导电层; 在基板上形成通过使用大直径抗蚀剂图案作为掩模通过蚀刻将第一导电层暴露在底部的大直径凹部; 在大直径凹部的形成范围内在基板上形成具有用于暴露第二导电层的上部的开口的小直径抗蚀剂图案; 以及在基板上形成小直径的凹部，其中通过使用小直径抗蚀剂图案作为掩模通过蚀刻将第二导电层暴露在底部。 版权所有（C）2013，JPO＆INPIT

公开(公告)号：JP2004311477A

公开(公告)日：2004-11-04

申请号：JP2003098780

申请日：2003-04-02

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUKAZAWA MASANAGA

IPC: H01L21/28 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device in which the occurrence of short circuiting between embedded wirings formed in wiring grooves can be prevented by suppressing the shoulder fall in the upper parts of the openings of the wiring grooves in a step of forming connection holes in the bottoms of the wiring grooves.
SOLUTION: In the method of manufacturing semiconductor device, first to fourth insulating films 4-7 and first to third mask layers 8-10 are formed on a substrate 3 in this order. Then openings 10a for grooves are formed in the third mask layer 10, connecting openings 12b for connection holes are formed in the first and second mask layers 8 and 9 and first to third insulating films 4-6 by performing etching by using a resist pattern 11 as a mask, and the pattern 11 is removed. Thereafter, openings for grooves are formed in the second and first mask layers 8 and 7 by performing etching from the above of the third mask layer 10. In addition, the wiring grooves are formed into the fourth insulating film 7 and, at the same time, connection holes are formed in the second insulating film 5 by performing etching from the above of the third and second mask layers 10 and 9, and the third mask layer 10 is etched off. Furthermore, connection holes are formed in the first insulating film 4 by performing etching from the above of the second and first mask layers 9 and 8.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004193326A

公开(公告)日：2004-07-08

申请号：JP2002359304

申请日：2002-12-11

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUKAZAWA MASANAGA

IPC: H01L23/522 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a wiring structure which enhances reliability on performances as well as yield of a semiconductor device by preventing the occurrence of diffusion between an interlayer dielectric and wiring, and to provide a method for manufacturing the same. SOLUTION: A wiring groove T is formed in an upper IMD (interlayer dielectric) 4 including a plurality of voids S, and the voids S which are exposed to the wiring groove T are each embedded with an insulating film 5, followed by embedding upper wiring 8 in the wiring groove T through a barrier film 7. Thus, since the voids S are not exposed to the wiring groove T in forming the barrier film 7, the barrier 7 is prevented from being formed with pinholes therein that would have been caused by the presence of the voids S exposed to the wiring groove T. In this way, the upper IMD 4 is physically separated from the upper wiring 8 by the barrier film 7, thereby preventing the occurrence of diffusion between the upper IMD 4 and the upper wiring 8 to ensure steady resistance characteristics of the semiconductor device. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2010139385A

公开(公告)日：2010-06-24

申请号：JP2008316130

申请日：2008-12-11

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KAWASHIMA ATSUSHI ,  TATSUMI TETSUYA ,  FUKAZAWA MASANAGA ,  KUBOI NOBUYUKI ,  NAGAHATA KAZUNORI

IPC: G01N21/71 ,  G01N21/00

Abstract: PROBLEM TO BE SOLVED: To provide a device for manufacturing a semiconductor device capable of detecting a substance remaining in an object to be analyzed, such as a chamber or a conveyance path of a semiconductor manufacturing device, and a device and method for analyzing a residual component.
SOLUTION: The device for analyzing a residual component includes an analysis object section (1) of a part constituting a manufacturing device of a semiconductor device in which a substrate is retained for a treatment process predetermined to manufacture semiconductors or a substrate is conveyed or stored in the before and after the treatment process, and also an analysis object of a residual component therein, a receiver 5 to receive an electromagnetic wave emitted from the residual component in the analysis object section, a spectroscopic section 6 to disperse a signal received by the receiver, in which a residual component in the analysis object section is analyzed by the dispersion in the manner.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于制造能够检测待分析物体中剩余的物质（例如半导体制造装置的室或输送路径）的半导体器件的装置，以及用于 分析残留成分。 解决方案：用于分析残余分量的装置包括构成半导体装置的制造装置的部件的分析对象部分（1），其中保持基板用于预定制造半导体的处理工艺或基板被传送 或存储在处理过程之前和之后，以及其中残留分量的分析对象;接收器5，用于接收从分析对象部分中的残余分量发射的电磁波;分光部分6，用于分散接收到的信号 由分析对象部分中的残差分量通过接收器以分散方式进行分析。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2007335621A

公开(公告)日：2007-12-27

申请号：JP2006165517

申请日：2006-06-15

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUKAZAWA MASANAGA

IPC: H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for semiconductor devices whereby a dual damascene structure can be formed whose formation accuracy is so good as to prevent the upper portions of its connection holes from shoulder-falling, and further, a highly reliable semiconductor device can be obtained whose void generation is prevented.
SOLUTION: The manufacturing method for semiconductor devices has a process for forming first of all an interlayer insulating film 5 on a substrate 1, a process for forming as a first mask a resist pattern 9 having connection-hole patterns above the interlayer insulating film 5, a process for forming next connection holes 5a in the interlayer insulating film 5 by etching performed from above the resist pattern (the first mask) 9, a process for forming thereafter a protective layer 21 in the state of covering with it the inner walls of the connection holes 5a, a process for forming next as a second mask on the interlayer insulating film 5 having the formed connection holes 5a a resist pattern having a wiring-groove pattern, a process for forming by the etching performed from above the second mask the wiring groove on the upper portion of the connection holes 5a whose inner walls are protected by the protective film 21, a process for exposing the substrate to the external in the bottoms of the connection holes 5a, and a process for forming thereafter an embedded wiring in the wiring groove and the connection holes 5a.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：为了提供一种半导体器件的制造方法，由此可以形成双镶嵌结构，其形成精度如此好以防止其连接孔的上部发生肩部下落，此外，高度 可以获得防止空隙产生的可靠的半导体器件。 解决方案：半导体器件的制造方法首先在衬底1上形成层间绝缘膜5的工艺，用于形成作为第一掩模的具有在层间绝缘层上方的连接孔图案的抗蚀剂图案9的工艺 膜5，通过从抗蚀剂图案（第一掩模）9上方进行的蚀刻在层间绝缘膜5中形成下一个连接孔5a的工艺，其后形成保护层21的方法， 连接孔5a的壁，在具有形成的连接孔5a的层间绝缘膜5上形成下一个作为第二掩模的工艺，具有布线槽图案的抗蚀剂图案，通过从第二个 遮蔽其内壁由保护膜21保护的连接孔5a的上部的布线槽，将基板暴露于底部的外部的工艺 s的连接孔5a，以及其后形成布线槽中的嵌入布线和连接孔5a的处理。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2001044191A

公开(公告)日：2001-02-16

申请号：JP21150199

申请日：1999-07-27

Applicant: SONY CORP

Inventor： IKEDA KOICHI ,  FUKAZAWA MASANAGA ,  KITO HIDEYOSHI ,  HASEGAWA TOSHIAKI

IPC: H01L21/302 ,  C08J7/00 ,  C08J7/04 ,  C08K3/04 ,  C08L83/04 ,  H01L21/3065 ,  H01L21/31 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To improve the performance of a semiconductor device, such as signal propagation delay, by reducing capacitance between interconnect layers and capacitance between interconnects while forming a silicon oxide film containing carbon on an organic insulating film. SOLUTION: A silicon oxide film 12 containing carbon is formed on an organic insulating film 11. Due to carbon present therein, the film 12 exhibits low relative permittivity while still holding the inorganic properties of a conventional silicon oxide film not containing an impurity such as carbon. Therefore, even when the insulating film having inorganic properties is formed on the film 11 having a low relative permittivity, lower relative permittivity can be achieved. Thus, a laminated insulating film 13 is interposed between interconnect layers and between interconnects, whereby capacitance between the interconnect layers and between the interconnects can be reduced, and this contributes to improving the performance of a semiconductor device, such as signal propagation delay.

公开(公告)号：JP2000252359A

公开(公告)日：2000-09-14

申请号：JP5577199

申请日：1999-03-03

Applicant: SONY CORP

Inventor： FUKAZAWA MASANAGA ,  KADOMURA SHINGO

IPC: H01L21/302 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

Abstract: PROBLEM TO BE SOLVED: To provide a method in which an insulating film including an organic dielectric film is etched and worked quickly without forming a damage layer and without lowering a throughput. SOLUTION: An insulating film 14 which contains an organic dielectric film such as a laminated film by an organic dielectric film 12 such as a polyallylether film or the like and by a silicon oxide-based dielectric film is formed on a substrate 10. A mask layer R is patterned and formed on the upper layer of the insulating film. Then, when the organic dielectric film part 12 is etched and worked, it is etched by making use of the mask layer as an etching mask by using ions or radicals which contain an NH group and which are generated by a gas discharge in a mixed gas of hydrogen gas and nitrogen gas or in a mixed gas of ammonia gas. While a reaction product containing a CN group is produced, the insulating film 14 (12) is etched, and an opening or the like is formed.