公开(公告)号：JP2000100829A

公开(公告)日：2000-04-07

申请号：JP27145998

申请日：1998-09-25

Applicant: SONY CORP

Inventor： IMOTO TSUTOMU ,  ISHIAI YOSHINORI ,  KAMATA MIKIO

IPC: H01L29/808 ,  H01L21/285 ,  H01L21/335 ,  H01L21/336 ,  H01L21/337 ,  H01L21/338 ,  H01L29/778 ,  H01L29/812

Abstract: PROBLEM TO BE SOLVED: To provide a junction field-effect transistor and a manufacturing method thereof, that can achieve low on-resistance, high maximum drain current, lineality with high transmitting gain, and a shorter gate, without the need for two kinds of positive and negative power sources. SOLUTION: An andoped GaAs layer 3, an n+-type GaAs layer 4, and an n-type GaAs layer 5 undergo epitaxial growth in this order via a GaAs buffer layer 2 on a semi-insulating GaAs substrate 1 to form a channel layer. A dispersion mask composed of SiNx film is formed on the n-type GaAs layer 5, and Zn is dispersed on the n-type GaAs layer 5 through the opening of the mask so as to form a p+-type gate region 6. A gate matallic layer is stacked on the dispersion mask and is patterned, so as to form a gate electrode 7 on the opening of the dispersion mask in a self-matching manner to the p+-type gate region 6.

公开(公告)号：JP2576524B2

公开(公告)日：1997-01-29

申请号：JP21474787

申请日：1987-08-28

Applicant: SONY CORP

Inventor： ISHIKAWA HIDETO ,  KAMATA MIKIO ,  KOBAYASHI TOSHIMASA

IPC: H01L21/205

公开(公告)号：JPH03218008A

公开(公告)日：1991-09-25

申请号：JP1312590

申请日：1990-01-23

Applicant: SONY CORP

Inventor： ISHIKAWA HIDETO ,  KAMATA MIKIO ,  SHIBATA HIROMASA

IPC: H01L21/205 ,  H01L21/338 ,  H01L29/778 ,  H01L29/812

Abstract: PURPOSE:To accurately control impurities doping by a method wherein undoped compound is vapor-grown, impurity gas is supplied in the state that growth is interrupted, and doping process is repeated until the surface density of carrier is nearly saturated. CONSTITUTION:Undoped compound is vapor-grown on a substrate 1, and an undoped compound semiconductor layer 12A having a specified thickness is formed. Next, in the state that the growth is interrupted, impurity material gas is supplied to the layer 12A, and doping is performed until the carrier surface density is nearly saturated, thereby forming an impurities doped layer 12B. By repeating this process several times, a compound semiconductor layer 12 is formed. Althorough, in this method, the impurity concentrations of all of the compound semiconductor layers take discrete values, each of the values is uniform, and uniform concentration can be realized all over the region of a wafer independently of wafer position. Hence impurities doping can be accurately controlled, and a device having specified characteristics can be surely obtained with superior reproducibility.

公开(公告)号：JPS6457711A

公开(公告)日：1989-03-06

申请号：JP21474787

申请日：1987-08-28

Applicant: SONY CORP

Inventor： ISHIKAWA HIDETO ,  KAMATA MIKIO ,  KOBAYASHI TOSHIMASA

IPC: H01L21/205

Abstract: PURPOSE:To reduce or annihilate N-type conduction on the interface of an epitaxial growth layer and an InP substrate by thermally treating the InP sub strate for thirty min or more at a growth temperature or more in a PH3 atmo sphere before growth, changing over PH3 to a reaction gas and starting vapor growth. CONSTITUTION:An InP substrate 1 is arranged onto a susceptor in a reaction tube, and the inside of the reaction tube is supplied with PH3 in a 20% hydrogen base and H2 gas as a carrier gas at normal pressure before growth. The InP substrate 1 is heated, the temperature of the substrate is kept at a vapor growth temperature of 640 deg.C, and the state is maintained for a fixed time and the supply of PH3 is stopped. The gas is changed over and the inside of the reaction tube is fed with a reaction gas composed of AsH3, trimethylpotassium and trimethylindium together with the carrier gas, and the growth of undoped GaInAs 4 is started. The holding time when the InP substrate is held in a PH3 atmosphere is increased while sheet carrier concentration No representing conduc tion on the interface 5 is reduced. When the holding time is lengthened to thirty min or more, sheet carrier concentration No can be diminished extremely or brought to zero.

公开(公告)号：JPS642364A

公开(公告)日：1989-01-06

申请号：JP15834487

申请日：1987-06-25

Applicant: SONY CORP

Inventor： KAMATA MIKIO

IPC: H01L29/78 ,  H01L21/338 ,  H01L29/778 ,  H01L29/80 ,  H01L29/812

Abstract: PURPOSE:To lower source resistance, to remove the limitation of a short channel effect and to manufacture an SISFET and a MISFET having a short channel with high accuracy by forming source and drain regions by the same semiconductor layer and dividing the source and drain regions by a second conductor layer (an insulating layer) brought into contact with a first semiconductor layer. CONSTITUTION:An undoped GaInAs layer 2 having a narrow band gap as a channel forming layer is epitaxial-grown onto a semi-insulating InP substrate 1 and an n -GaInAs layer 13 in specified thickness as a source region and a drain region onto the layer 2. The layer 13 corresponding to a gate is etched selectively, and etched so as to be intruded into the layer 2. The source region 14 and the drain region 15 are shaped through said etching. An undoped AlInAs layer 3 as an insulating layer and an n -GaInAs layer 4 having specified thickness as a gate electrode are grown through second epitaxial growth, and a photo-resist 18 is buried into a recessed section 17 corresponding to a gate section of the layer 4.

公开(公告)号：JPS6323384A

公开(公告)日：1988-01-30

申请号：JP16757686

申请日：1986-07-16

Applicant: SONY CORP

Inventor： KAMATA MIKIO ,  ISHIKAWA HIDETO ,  HONDA KAZUO

IPC: H01S5/00 ,  H01S5/32

Abstract: PURPOSE:To permit a sufficient confinement of light by a method wherein the energy band gap between an active layer on one side on a conduction band side or a valence band side and a first clad layer is made larger than that between the active layer and a second clad layer. CONSTITUTION:An active layer 9 is a Ga0.47In0.53As layer having an energy gap of 0.75 eV, a P-type clad layer 4 is an Al0.48In0.52As layer having an energy gap of 1.45 eV and an n-type clad layer 3 is an InP layer having an energy gap 1.35 eV. AP GaInAsP layer 5 is a region for making a contact and connected to ohmic electrodes 7 through a striped window in an insulating layer 6 provided thereon. By forming the ohmic electrodes into a striped form, the region where current flows is made narrower and the threshold current can be made lower. An ohmic electrode 1 on the other side is formed on an n-type InP substrate 2. When current is caused to flow in the forward direction, minority carriers are injected from the clad layers and confined in the active layer and a recombination of electrons and holes is generated therein and light is emitted in the direction shown by an arrow.

公开(公告)号：JPS6151876A

公开(公告)日：1986-03-14

申请号：JP17359384

申请日：1984-08-21

Applicant: Sony Corp

Inventor： KAMATA MIKIO

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/0847

Abstract: PURPOSE:To improve the degree of integration, and to simplify manufacture by forming several first conduction type first source and drain region and several second conduction type second source and drain region to a common high-resistivity semiconductor layer while holding a common insulated gate section shaped to the common semiconductor layer. CONSTITUTION:A compound semiconductor base body So as a high-resistivity semiconductor layer 1 is formed, and N type and P type first source and drain regions 3 and 4 and second source and drain regions 5 and 6 are each shaped onto one main surface of the base body while an oxide gate insulating layer 11 is formed to the surface of the base body not coated with impurity layers 10N and 10P, particularly, a facing section among respective region 3, 4, 5, 6 shaping a final gate section. A gate electrode 12 is formed. Electrode windows are bored to the silicate glass layers 10N and 10P on each region 3, 4, 5, 6, and a first wiring layer 13 to which source or drain several electrode or wirings are shaped respectively is formed. An inter-layer insulating layer 14 is shaped onto the whole surface, a window is bored to the insulating layer 14, and a wiring layer 15 electrically connected to the gate electrode 12 is evaporated onto the whole surface, and patterned.

Abstract translation: 目的：为了提高集成度，并通过将多个第一导电类型的第一源极和漏极区域以及多个第二导电类型的第二源极和漏极区域形成到公共高电阻率半导体层来简化制造，同时保持共同的绝缘栅极截面形状 到公共半导体层。 构成：化合物半导体基体作为高电阻率半导体层1，形成N型和P型第一源极和漏极区域3以及第二源极和漏极区域5和6各自的一个主表面上， 基体，而氧化物绝缘层11形成在未涂覆有杂质层10N和10P的基体的表面上，特别是形成最终栅极部分的各个区域3,4,5,6之间的面对部分。 形成栅电极12。 电极窗口在每个区域3,4,5,6上的硅酸盐玻璃层10N和10P以及分别形成有多个电极或布线的源极或漏极的第一布线层13形成。 在整个表面上形成层间绝缘层14，将窗口钻到绝缘层14上，并且电连接到栅电极12的布线层15蒸发到整个表面上并被图案化。

公开(公告)号：JPS6149477A

公开(公告)日：1986-03-11

申请号：JP17118484

申请日：1984-08-17

Applicant: Sony Corp

Inventor： KAMATA MIKIO ,  WATANABE SEIICHI

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/201 ,  H01L29/43 ,  H01L29/778 ,  H01L29/80

CPC classification number: H01L29/432

Abstract: PURPOSE:To select threshold voltage within a wide range by constituting a semiconductor layer constituting a hetero-junction, which does not function as a channel forming section, by a nonsingle crystal body in double-hetero constitution. CONSTITUTION:A first semiconductor layer 1 in low impurity concentration and a second semicondutor layer 2, to which an impurity is not doped or an impurity such as an n type one is doped, on the layer 1 are formed to shape a first hetero-junction JHI. A third semiconductor layer 3 in high impurity concentration forming a second hetero-junction JHII between the layer 2 and itself is shaped brought into contact with the layer 2, and a channel 4 by a two demensional electron gas is formed on the layer 1 side of the junction JHI. The layer 3 is shaped by a nonsingle crystal semiconductor such as polycrystalline or amorphous semiconductor. Accordingly, since the layers are not grown in an epitaxial manner as single crystals, a material, for which a lattice constant is considered, need not be selected, thus improving the degree of freedom on the selection of threshold voltage.

Abstract translation: 目的：通过构成不是作为通道形成部的异质结的半导体层，通过双异质结构的非单晶体来选择宽范围内的阈值电压。 构成：在层1上形成低杂质浓度的第一半导体层1和不掺杂杂质的第二半导体层2或杂质例如n型杂质，形成第一异质结 JHI。 在层2和本身之间形成第二异质结JHII的高杂质浓度的第三半导体层3成形为与层2接触，并且通过两维电子气形成通道4在第一层 JHI连接点。 层3由诸如多晶或非晶半导体的非单晶晶体半导体形成。 因此，由于层不以单晶的外延生长，所以不需要选择晶格常数的材料，因此提高阈值电压选择的自由度。

公开(公告)号：JPS6135567A

公开(公告)日：1986-02-20

申请号：JP15803584

申请日：1984-07-27

Applicant: Sony Corp

Inventor： KAMATA MIKIO

IPC: H01L29/812 ,  H01L21/338 ,  H01L27/06 ,  H01L29/205 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L29/7787 ,  H01L27/0611

Abstract: PURPOSE:To compose, for instance an inverter circuit or a charge transfer device with an eminent high speediness by combining a HEMT with a DH-MIS- FET. CONSTITUTION:The first and the second electric field effect transistor portions 35 and 36 are provided in a common semiconductor substrate having the relation inwhich levels EC1, EC2 and EC3 of a conduction band bottom is shown as EC1

Abstract translation: 目的：通过将HEMT与DH-MIS-FET组合，来组成例如具有显着的高速度的逆变器电路或电荷转移装置。 构成：将第一和第二电场效应晶体管部分35和36设置在具有这样的关系的公共半导体衬底中，其中导带底部的EC1，EC2和EC3的电平被表示为EC1

公开(公告)号：JPS56160082A

公开(公告)日：1981-12-09

申请号：JP5381180

申请日：1980-04-23

Applicant: SONY CORP

Inventor： HIRATA YOSHIMI ,  KAMATA MIKIO ,  SHIMADA TAKASHI

IPC: H01L27/148 ,  H04N5/335 ,  H04N5/3725

Abstract: PURPOSE:To enlarge a light receiving area and make it high density by a method wherein an insulation layer is formed on a semiconductor substrate, the first gate electrodes being formed on the insulation layer surface and further, a barrier region, an oxide film and the second gate electrodes being formed. CONSTITUTION:The insulation layer 2 is formed on one main surface of the silicon semiconductor substrate 1 and the first gate electrodes 3 are attach-formed on the surface of the layer 2 so as to be arranged in parallel in belt-shape. The plurality of the second gate electrodes 4 are attach-formed in belt-shape on the insulation layer 2 between the first gate electrodes 3. The barrier region 6 is formed on the substrate surface under the each second gate electrode 4. The first gate electrodes 3 and the second gate electrodes 4 constitute transfer electrodes 5 respectively, the respective first gate electrodes 3 being connected in common at the ends every other one, and the image pickup unit is constructed in such that clock signals are applied between the two pairs of the electrodes 5.