公开(公告)号：FR2835652A1

公开(公告)日：2003-08-08

申请号：FR0201305

申请日：2002-02-04

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  CHANTRE ALAIN

IPC: H01L21/8249

Abstract: When the fabrication of the insulated gate field effect transistor is started, then the bipolar transistor (BIP1,BIP2) is totally fabricated, before the resumption of fabrication of the insulated gate field effect transistor (MOS), and the step of common finishing of the two transistors is executed, including the common thermal reheating treatment (122) and common silication treatment.

公开(公告)号：FR2799048B1

公开(公告)日：2003-02-21

申请号：FR9911895

申请日：1999-09-23

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HELENE

IPC: H01L29/73 ,  H01L21/205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L29/737 ,  H01L21/00 ,  H01L21/22 ,  H01L29/732

Abstract: Bipolar transistor fabrication includes a step of producing a base region (8) comprising an extrinsic base (800) and an intrinsic base, and a step of producing an emitter block having a narrower lower part located in an emitter-window above the intrinsic base. Production of the extrinsic base (800) involves dopant implantation after defining the emitter-window, on both sides at a determined distance from the lateral limits of the emitter-window, with self-alignment about the emitter-window, and before emitter block formation. An oxide block (13) is formed on an insulating layer located above the intrinsic base. The oxide block (13) has a narrower lower part (130) located in an etched hole of the insulating layer and whose dimensions correspond to those of the emitter-window, and an upper wider part (131) resting on the insulating layer. The lateral sides of the etched hole of the insulating layer are self-aligned with the lateral sides (FV) of the upper part of the oxide block. Ion implantation of the extrinsic base is formed on both sides of the upper part of the oxide block (13).

公开(公告)号：FR2813707B1

公开(公告)日：2002-11-29

申请号：FR0011419

申请日：2000-09-07

Applicant: ST MICROELECTRONICS SA

Inventor： DUTARTRE DIDIER ,  CHANTRE ALAIN ,  MARTY MICHEL ,  JOUAN SEBASTIEN

IPC: H01L21/331 ,  H01L29/10 ,  H01L21/28

Abstract: A method of manufacturing a bipolar transistor in a single-crystal silicon substrate of a first conductivity type, including a step of carbon implantation at the substrate surface followed by an anneal step, before forming, by epitaxy, the transistor base in the form of a single-crystal semiconductor multilayer including at least a lower layer, a heavily-doped median layer of the second conductivity type, and an upper layer that contacts a heavily-doped emitter of the first conductivity type.

公开(公告)号：FR2801420B1

公开(公告)日：2002-04-12

申请号：FR9914746

申请日：1999-11-23

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  DUTARTRE DIDIER ,  CHANTRE ALAIN ,  JOUAN SEBASTIEN ,  LLINARES PIERRE

IPC: H01L21/331 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/737 ,  H01L29/732

Abstract: Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector on a layer of extrinsic collector in a semiconductor substrate; (b) making a lateral isolating region; (c) making a base next to he intrinsic collector and the lateral isolating region; and (d) making a bipartite dope emitter in situ. Preparation of a bipolar vertical transistor comprises: (a) making an intrinsic collector (4) on a layer of extrinsic collector (2) in a semiconductor substrate (1); (b) making a lateral isolating region (5) surrounding the upper part of the intrinsic collector and of wells of the imprisoned extrinsic collector (60); (c) making a base (8) next to he intrinsic collector and the lateral isolating region and comprising a non-selective epitaxy of a semiconductor region (8) comprising at least one layer of silicon; (d) making a bipartite dope emitter (11) in situ comprising: (i) making a first layer (110) of the emitter formed from microcrystalline silicon and directly in contact with a part (800) of the upper surface of the semiconductor region situated on top of the intrinsic collector; and (ii) making a second part (111) of emitter from polycrystalline silicon; the two parts (110, 111) being separated by an oxide layer (112).

公开(公告)号：FR2779573B1

公开(公告)日：2001-10-26

申请号：FR9807061

申请日：1998-06-05

Applicant: ST MICROELECTRONICS SA

Inventor： MARTY MICHEL ,  CHANTRE ALAIN ,  REGOLINI JORGE LUIS

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/08 ,  H01L29/10 ,  H01L29/737 ,  H01L29/732

Abstract: The bipolar transistor comprises a base (Be) of heterojunction silicon-germanium. The base is in block (8) of layers of silicon and silicon-germanium on an initial layer (17) of silicon nitride spread on a region with lateral isolation (5). An internal collector (4) is enclosed and situated inside a window in the layer of silicon nitride. The fabrication process includes the growth of a layer of silicon dioxide on a block of semiconductor. A layer of silicon nitride (Si3N4) is then deposited, and etched until the layer of silicon dioxide. A chemical process is used to remove a portion of the layer of silicon dioxide within the window. The layer of silicon nitride has a thickness of about 300 Angstrom, and that of silicon dioxide about 200 Angstrom.

公开(公告)号：FR2805923A1

公开(公告)日：2001-09-07

申请号：FR0002855

申请日：2000-03-06

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  BAUDRY HELENE

IPC: H01L21/331

Abstract: The process includes successively forming, over a base region of a semiconductor substrate, a poly-Ge or poly-SiGe layer, an etch-stop layer over a selected zone of the Ge or SiGe layer, a layer of poly-Si of the same conductivity type as the base region, then an outer layer of dielectric material. Etching the layers includes stopping at the stop layer to form an emitter window preform, removing the stop film and selectively removing the Ge or SiGe layer in the emitter window preform to form an emitter window and to form an emitter made of poly-Si of conductivity type the opposite of the base region in the window.

公开(公告)号：FR2858877B1

公开(公告)日：2005-10-21

申请号：FR0350418

申请日：2003-08-11

Applicant: ST MICROELECTRONICS SA

Inventor： MARTINET BERTRAND ,  MARTY MICHEL ,  CHEVALIER PASCAL ,  CHANTRE ALAIN

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737

Abstract: A method for forming a heterojunction bipolar transistor including the steps of: forming in a semiconductor substrate a collector area of a first doping type; growing by epitaxy above a portion of the collector area a silicon/germanium layer of a second doping type forming a base area; forming above the silicon/germanium layer a sacrificial emitter formed of a material selectively etchable with respect to the silicon/germanium layer and with respect to the layers and consecutively-formed insulating spacers; forming first insulating spacers on the sides of the sacrificial emitter; growing by epitaxy a silicon layer above the exposed portions of the silicon/germanium layer; forming second insulating spacers adjacent to the first spacers and laid on the silicon layer; covering the entire structure with an insulating layer; partially removing the insulating layer above the sacrificial emitter and removing the sacrificial emitter; filling the space previously taken up by the sacrificial emitter with a semiconductor material of the first doping type.

公开(公告)号：FR2868206A1

公开(公告)日：2005-09-30

申请号：FR0450609

申请日：2004-03-29

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  CHEVALIER PASCAL

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/423 ,  H01L29/73 ,  H01L29/732

Abstract: L'invention concerne un transistor bipolaire réalisé dans un substrat semiconducteur (20) d'un premier type de conductivité, comportant, directement sur le substrat, une région semiconductrice monocristalline (34) dopée d'un second type de conductivité délimitée par un isolant (30) et immédiatement sous-jacente à une couche semiconductrice monocristalline (26) dopée du second type de conductivité constituant la base extrinsèque du transistor, ladite base extrinsèque monocristalline s'étendant également sur ledit isolant, un émetteur (19) du transistor étant formé sur ladite région semiconductrice monocristalline et étant isolé de ladite base extrinsèque monocristalline.

公开(公告)号：FR2779572B1

公开(公告)日：2003-10-17

申请号：FR9807059

申请日：1998-06-05

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  MARTY MICHEL ,  DUTARTRE DIDIER ,  MONROY AUGUSTIN ,  LAURENS MICHEL ,  GUETTE FRANCOIS

IPC: H01L21/331 ,  H01L29/08 ,  H01L29/737 ,  H01L29/73 ,  H01L29/732

Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

公开(公告)号：FR2822292B1

公开(公告)日：2003-07-18

申请号：FR0103469

申请日：2001-03-14

Applicant: ST MICROELECTRONICS SA

Inventor： CHANTRE ALAIN ,  BAUDRY HELENE ,  DUTARTRE DIDIER

IPC: H01L21/331 ,  H01L29/737