公开(公告)号：FR2801751A1

公开(公告)日：2001-06-01

申请号：FR9915115

申请日：1999-11-30

Applicant: ST MICROELECTRONICS SA

Inventor： POMET ALAIN ,  PLESSIER BERNARD ,  SOURGEN LAURENT

IPC: H04L9/20 ,  H04L9/00 ,  H04L9/08 ,  H04L9/10

Abstract: The electronic component has a bidirectional bus (DATA BUS) passing digital words between peripherals (P1,P2,P3) and a central unit (CPU) and having cascaded clock signals (PMI). The central unit and peripherals have encryption and encryption cells (Kcell) of the digital words with a secret key. A current value of the secret key is produced each clock cycle as part of a random signal (Kin) and applied to the cells by the transmission line.

公开(公告)号：FR2790345B1

公开(公告)日：2001-04-27

申请号：FR9902365

申请日：1999-02-25

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE YVAN ,  ROMAIN FABRICE ,  PLESSIER BERNARD ,  HENNEBOIS BRIGITTE

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30 ,  H04L9/00

Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.

公开(公告)号：FR2790345A1

公开(公告)日：2000-09-01

申请号：FR9902365

申请日：1999-02-25

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE YVAN ,  ROMAIN FABRICE ,  PLESSIER BERNARD ,  HENNEBOIS BRIGITTE

IPC: H04L9/06 ,  H04L9/08 ,  H04L9/30 ,  H04L9/00

Abstract: The secure coprocessor encryption technique has a memory module (30) and a battery of input/output registers (32). A multiplexer (34) transfers the digital words between the input/output register and the input register (36). There is a key register (38) and processing module (42). The battery of input/output registers has an external noise interference register (50) showing when the encryption/de encryption and digital key are at risk.

公开(公告)号：FR2788865A1

公开(公告)日：2000-07-28

申请号：FR9900988

申请日：1999-01-27

Applicant: ST MICROELECTRONICS SA

Inventor： PLESSIER BERNARD ,  POMET ALAIN

IPC: G06F7/72 ,  G11C7/10 ,  H03M9/00

Abstract: A first k bit shift register (150) has a parallel input and a series output. The parallel input is connected to an input of a first flip-flop circuit (155). A second k bit flip-flop circuit (159) has a parallel input and a parallel output. The latter is connected to a data bus (161). A second k bit shift register (154) has a serial input and a parallel output. The latter is connected to the input of the flip-flop circuit (159). An Independent claim is included for: (a) a coprocessor

公开(公告)号：FR2801751B1

公开(公告)日：2002-01-18

申请号：FR9915115

申请日：1999-11-30

Applicant: ST MICROELECTRONICS SA

Inventor： POMET ALAIN ,  PLESSIER BERNARD ,  SOURGEN LAURENT

IPC: H04L9/20 ,  H04L9/00 ,  H04L9/08 ,  H04L9/10

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

公开(公告)号：DE69802016D1

公开(公告)日：2001-11-15

申请号：DE69802016

申请日：1998-08-26

Applicant: ST MICROELECTRONICS SA

Inventor： PLESSIER BERNARD

IPC: G06F7/52 ,  G06F7/72 ,  G06F7/76

Abstract: At least one shift register (17) receives at least one word of Bt bits of the dividend and performs Bt shifts of Bt-1 bits with input and output connected via multiplexer (16) to output the word in reverse order. At least one shift register (22) receives at least one word of Bt bits of the quotient and performs a similar series of shifts with a multiplexer (21) to output the word in reverse order. An Independent claim is also included for the modular arithmetic coprocessor.

公开(公告)号：FR2788865B1

公开(公告)日：2001-10-05

申请号：FR9900988

申请日：1999-01-27

Applicant: ST MICROELECTRONICS SA

Inventor： PLESSIER BERNARD ,  POMET ALAIN

IPC: G06F7/72 ,  G11C7/10 ,  H03M9/00

公开(公告)号：FR2794258A1

公开(公告)日：2000-12-01

申请号：FR9906743

申请日：1999-05-26

Applicant: ST MICROELECTRONICS SA

Inventor： POMET ALAIN ,  PLESSIER BERNARD

IPC: G06F7/52 ,  G06F7/544

Abstract: A selection device (22o-22a-1) and (23o-23a-1) provides either '0' and '0', or '0' and A, or A and '0', or A and A, on first and second according to even and odd bit of B. An accumulator (24-28) and (29o-29a-i) is connected to the first and second outputs to add the data from first and second outputs to an accumulated result. An Independent claim is included for: (a) a method of multiplying of two numbers