公开(公告)号：FR2831289B1

公开(公告)日：2004-01-23

申请号：FR0113478

申请日：2001-10-19

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  BASSET PHILIPPE

IPC: G06F9/30 ,  G06F9/32 ,  G06F9/34 ,  G06F9/355 ,  G06F12/02 ,  G06F9/44 ,  G06F15/00

Abstract: A microprocessor includes a processing unit, an address bus connected to an addressable memory space, and executes instructions from an instruction set for accessing the addressable memory space. The addressable memory space is for a lower memory area and an extended memory area. The instruction set includes a first instruction group for accessing the lower memory area, and a second instruction group that is distinct from the first instruction group for accessing the extended memory area.

公开(公告)号：FR2831288A1

公开(公告)日：2003-04-25

申请号：FR0113412

申请日：2001-10-18

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  COLOMB ANDRE

IPC: G06F9/315 ,  G06F9/318 ,  G06F9/44

Abstract: A microprocessor has internal registers (A, X, Y), an arithmetic logic unit (ALU) and reads a program memory to execute an instruction set having a supplementary instruction for commanding the exchange of the memory or register contents. The microprocessor has an additional internal register (17) with means for exchanging the contents of the second register with the internal register. The invention also relates to a microprocessor with two additional internal registers.

公开(公告)号：FR2817362B1

公开(公告)日：2003-01-24

申请号：FR0015390

申请日：2000-11-29

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  BOUQUIER THIERRY

IPC: G06F11/267 ,  G06F11/30 ,  G06F9/06 ,  G06F12/00 ,  G06F11/36

Abstract: Microprocessor (MP2) includes a device (CPU) to protect contextual data (CCo,Ao,Xo,PCho,PCIo) in its stack (STK) at the time of a interruption of a test program. A delivery device brings a data (CCo,Ao) present in the stack (STK) to an I/O port of the microprocessor at the beginning of a test session starting at the top of the stack. A pointer of the stack (SP) is decremented by a value corresponding to the number of delivered contextual data. An Independent claim is included for: (a) a method of managing a memory space of the microprocessor after the interruption by a test program for registering context data in a stack

公开(公告)号：FR2821456A1

公开(公告)日：2002-08-30

申请号：FR0102701

申请日：2001-02-28

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  CAVALLI DIDIER

IPC: G06F12/06 ,  G06F13/16 ,  G06F13/36 ,  G06F13/40 ,  G06F15/76 ,  G06F13/368

Abstract: The invention relates to a microprocessor which is connected to a first memory space (4) by means of a first bus (AP, DIP, DOP, RWP) and to a second memory space (5) by means of a second bus (AD, DID, DODD, RWD). The inventive microprocessor comprises a processing unit (2), which is fitted with a program bus (PC, INS) and a data bus (A, DBO, DBI, RW), and an interface unit (3) which is connected, on one side, to the program bus (PC, INS) and the data bus (A, DBO, DBI, RW) and, on the other side, to the first bus (AP, DIP, DOP, RWP) and the second bus (AD, DID, DOP, RWD). The interface unit (3) comprises switching means (23, 25, 26) for connecting the program bus and the data bus respectively either to the first bus or the second bus according to the requests sent by the processing unit for access to the program (NPR) and to the data (NDR) respectively.

公开(公告)号：FR2789501B1

公开(公告)日：2001-04-13

申请号：FR9901517

申请日：1999-02-09

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK

IPC: G06F1/32

Abstract: A method and device reduces consumption of a microcontroller, allowing the microcontroller to enter into an "active halt" mode in which the central processing unit, the internal peripheral circuits, and a clock tree are deactivated. The main oscillator is operative and delivers an oscillating signal. An internal interruption returns the microcontroller back into the run mode and is generated after a time delay obtained by an internal circuit activated by the oscillating signal.

公开(公告)号：DE602004007835D1

公开(公告)日：2007-09-13

申请号：DE602004007835

申请日：2004-01-14

Applicant: ST MICROELECTRONICS SA

Inventor： PADMANABHA GOSAGAN ,  DAVIDESCU DRAGOS ,  ROCHE FRANCK

IPC: G06F9/38 ,  G06F9/06 ,  G06F9/30 ,  G06F9/42 ,  G06F9/46 ,  G06F11/30 ,  G06F12/16

Abstract: The microprocessor has a CPU with registers containing a contextual data and a pointer of stack (SP, SPH, SPL). A memory (MEM2) has a stack (STK) for backup of the contextual data. The CPU is arranged to backup the contextual data contained in a variable number of registers according to a flag value stored in a register (CCR, CR) to backup, at a time of shifting from one program to another. An independent claim is also included for a process of management of stack of microprocessor.

公开(公告)号：FR2831288B1

公开(公告)日：2004-12-10

申请号：FR0113412

申请日：2001-10-18

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  COLOMB ANDRE

IPC: G06F9/315 ,  G06F9/318 ,  G06F9/44

Abstract: A microprocessor includes internal registers, an arithmetic and logic unit, and reads a program memory and executes an instruction set stored therein. The instruction set includes at least one instruction for exchanging the contents of both memory locations. The microprocessor includes an additional internal register connected to an output of the arithmetic and logic unit, and transfers the contents of a first one of the memory locations to be exchanged into the additional register when executing the instruction set. The microprocessor further transfers the contents of a second one of the memory locations to be exchanged into the first memory location, and transfers the contents of the additional register into the second memory location.

公开(公告)号：FR2851349A1

公开(公告)日：2004-08-20

申请号：FR0301879

申请日：2003-02-17

Applicant: ST MICROELECTRONICS SA

Inventor： PADMANABHAN GOSAGAN ,  DAVIDESCU DRAGOS ,  ROCHE FRANCK

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/38 ,  G06F9/42 ,  G06F9/46 ,  G06F11/30 ,  G06F12/16

Abstract: The microprocessor has a CPU with registers containing a contextual data and a pointer of stack (SP, SPH, SPL). A memory (MEM2) has a stack (STK) for backup of the contextual data. The CPU is arranged to backup the contextual data contained in a variable number of registers according to a flag value stored in a register (CCR, CR) to backup, at a time of shifting from one program to another. An independent claim is also included for a process of management of stack of microprocessor.

公开(公告)号：FR2850176A1

公开(公告)日：2004-07-23

申请号：FR0300442

申请日：2003-01-16

Applicant: ST MICROELECTRONICS SA

Inventor： LENDRE SANDRINE ,  PLOURDE OLIVIER ,  ROCHE FRANCK

IPC: G06F1/04 ,  G06F1/12

Abstract: The circuit has a decounter (DCNT) producing a time base signal (TBS) from a clock signal (H1) and count value (TBVAL1). A counter, register, and logic circuit (CNT,CREG,CCT) find another count value (TBVAL2) equal to a number of periods of another clock signal (H2) appearing during a time interval equal to periods of the signal (TBS). The decounter produces another time base signal from the signal (H2) and value (TBVAL2).

公开(公告)号：FR2820523B1

公开(公告)日：2003-05-16

申请号：FR0101681

申请日：2001-02-08

Applicant: ST MICROELECTRONICS SA

Inventor： ROCHE FRANCK ,  LAFARGUE NICOLAS

IPC: G06F5/01 ,  G06F7/575 ,  G06F7/76 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315

Abstract: A microprocessor comprises a central processing unit having an arithmetic and logic unit with two inputs and one input fed-back to one of the inputs through a data path. The arithmetic and logic unit performs arithmetic and logic operations on binary words temporarily stored within registers in the central processing unit. The central processing unit further includes a shift unit in the data path of the arithmetic and logic unit for performing operations to shift bits in the binary words applied thereto. A selection circuit selects a shift operation to be performed. An inverting circuit inverts the ordering of the bits in the binary words applied thereto, which are in the data path of the arithmetic and logic unit, and a selection circuit selects the inversion operation when the latter is required.