公开(公告)号：FR2871282A1

公开(公告)日：2005-12-09

申请号：FR0406077

申请日：2004-06-04

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE ,  FOURNEL RICHARD

IPC: G11C17/08 ,  G11C17/16

Abstract: Un dispositif mémoire à deux bits programmable une seule fois, comprend un transistor MOS de stockage ayant un substrat semiconducteur, une première et une seconde zones actives réalisées sous la surface du substrat en étant séparées par une partie du substrat formant zone de canal, une grille réalisée à la surface dudit substrat au droit de la zone de canal et dont des extrémités distales respectives viennent au droit d'une partie de la première zone active et d'une partie de la seconde zone active respectivement, et portée en permanence à un potentiel de masse, et une couche d'oxyde de grille s'étendant entre la grille et la surface du substrat, dont l'état intact ou claqué entre la grille et la première zone active détermine la valeur stockée d'un premier bit, et dont l'état intact ou claqué entre la grille et la seconde zone active détermine la valeur stockée d'un second bit.

公开(公告)号：FR2849962A1

公开(公告)日：2004-07-16

申请号：FR0300307

申请日：2003-01-13

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/07 ,  H01L27/11 ,  H01L29/94 ,  H01L29/92 ,  H01L27/108

Abstract: The capacitor has an electrode constituting an active region (D) strongly doped from a semiconductor component formed from the side of a surface of a semiconductor body. Another electrode constitutes a conducting region (BR) enclosed by an insulator (IL) formed beneath the active region and embedded in the body. The conducting region has an extension from which a contact opening is formed towards the latter electrode. Independent claims are also included for the following: (a) SRAM memory cell (b) a manufacturing procedure for a capacitor.

公开(公告)号：FR2833783B1

公开(公告)日：2004-03-12

申请号：FR0116072

申请日：2001-12-13

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE ,  JACQUET FRANCOIS ,  ROCHE PHILIPPE

IPC: G11C11/412 ,  H01L27/11 ,  H03K3/037 ,  H03K19/08

Abstract: The integrated circuit has a first (C1) and second (C2) capacitor connected in series between a first and second node. A control wire (450) is connected to the common point between the two capacitors.

公开(公告)号：FR2787240B1

公开(公告)日：2002-08-09

申请号：FR9815769

申请日：1998-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE ,  GAYET PHILIPPE

IPC: H01L21/02 ,  H01L21/768 ,  H01L21/4763 ,  H01L21/8239

Abstract: Four transistors is formed in a semiconductor substrate and interconnected by a local interconnection layer (M0) situated under a first metallisation level (M1). Two resistances (LIL1,LIL2) provides local interconnection layer between the metallisation layer (M0) and the first metallisation level (M1). An Independent claim is included for: (a) a method of formation of integrated circuit disposed on two levels of metallisation

公开(公告)号：FR2794895A1

公开(公告)日：2000-12-15

申请号：FR9907429

申请日：1999-06-11

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE

IPC: G11C11/56 ,  H01L21/8246 ,  H01L27/112

Abstract: The read-only memory cell (CM1) has a memory transistor in a semiconductor substrate. The source (S1) is connected to earth, the first metallised line (WL12) to grid (G1) and several auxiliary metallic lines (BL0,BL1,BL2) are connected to the drain (D1) of the transistor.

公开(公告)号：FR2849962B1

公开(公告)日：2005-09-30

申请号：FR0300307

申请日：2003-01-13

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE

IPC: H01L21/02 ,  H01L21/8244 ,  H01L27/07 ,  H01L27/11 ,  H01L29/94 ,  H01L29/92 ,  H01L27/108

Abstract: The capacitor has an electrode constituting an active region (D) strongly doped from a semiconductor component formed from the side of a surface of a semiconductor body. Another electrode constitutes a conducting region (BR) enclosed by an insulator (IL) formed beneath the active region and embedded in the body. The conducting region has an extension from which a contact opening is formed towards the latter electrode. Independent claims are also included for the following: (a) SRAM memory cell (b) a manufacturing procedure for a capacitor.

公开(公告)号：FR2851371B1

公开(公告)日：2005-06-03

申请号：FR0301937

申请日：2003-02-18

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE ,  JAOUEN HERVE

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/76

Abstract: The method involves hollowing a space (8) in an electronic circuit to form an electric connection between conducting parts of the circuit. A lithographic mask with an opening stumbling across the space is formed on the circuit. An electrical isolating material (12) is deposited on a part found by the mask to partially fill the space. The material is withdrawn such that the space is partially filled with the material. An independent claim is also included for an integrated electronic circuit.

公开(公告)号：FR2840445B1

公开(公告)日：2004-09-10

申请号：FR0206794

申请日：2002-06-03

Applicant: ST MICROELECTRONICS SA

Inventor： JACQUET FRANCOIS ,  SCHOELLKOPF JEAN PIERRE

IPC: G06F11/10 ,  G11C29/00 ,  H04L1/22

Abstract: The memory circuit equipped with a system for error correction comprises an address (ADD) bus (102), an input data (DIN) bus (108), an output data (Dout) bus (115), a memory store (100) with an address bus (113), an input data (DinSP) bus (114), and an output data (DoutSP) bus (110), and a circuit for error correction comprising an encoder (107). The memory circuit also comprises an address register (104) connected to the address bus (102) and storing the addresses corresponding only to the write operations in the memory, a data register (105) connected to the input data bus (108) for storing the data transmitted to the encoder (107), and a multiplexer (103) allowing to introduce a shift of a cycle in the write operation without modifying the read operation, in a manner to permit a longer computing time for the encoder. The memory store (100) is RAM with single port (SP) and comprises an internal address register (101) and an internal data register (106). The multiplexer (103) comprises two inputs, one connected to the address bus (102) and the other to the output of the address register (104), a single output connected to the address bus (102) and the other to the output of the address register (104), a single output connected to the address bus (113) of the memory store (100), and a control input for a Write Enable Negative (WEN) signal, that is for authorizing the write operation. The memory circuit also comprises a comparator (109) with two inputs, one connected to the address bus (102) and the other to the output of the address register (104), and a single output (112) connected to the control input of the second multiplexer (111) with two inputs, one connected to the output of the data register (105) and the other to the output data bus (110) of the memory store (100), and a single output connected to the output data bus (115). The memory circuit (claimed) is in three embodiments. In the second embodiment, the memory circuit comprises an additional memory store which is double-port, and an ECC decoder. In the third embodiment, the memory circuit comprises a synchronous static memory store which is single-port, and an ECC decoder. The memory circuit comprises a synchronous static memory. The memory circuit comprises a system for error correction of type Single Error Correction Double Error Detection (SEC-DED) or Double Error Correction, Triple Error Detection (DEC-TED).

公开(公告)号：FR2840443A1

公开(公告)日：2003-12-05

申请号：FR0206863

申请日：2002-06-04

Applicant: ST MICROELECTRONICS SA

Inventor： FOURNEL RICHARD ,  SCHOELLKOPF JEAN PIERRE ,  CANDELIER PHILIPPE

IPC: G11C8/12 ,  G11C16/08 ,  G11C7/22

Abstract: The memory element comprises a set of n memory units (10-1,....,10-n), each with an address bus, a data bus, and a control bus connected respectively to the main address bus, the main data bus and the main control bus. The memory units comprise the elements of fuse/antifuse type allowing an irreversible registering of information. The control chain comprises the selection units (12-1,....,12-n) each generating a selection signal, that is a Chip-Select (CSi), where i is from 1 to n, for one of the memory units (10i) in a manner to allow an exclusive access to the selected memory unit. The selection units switch automatically the selection of memory units following the detection of a predetermined condition. The memory element allows to implement an equivalent of a programmable memory of the type few times programmable (FTP), and in particular of type FLASH. A memory circuit (claimed) comprises the memory units of programmable type. The memory element comprises the programmable memory units (10-1,...,10-n) each receiving a Status Bit (SBi) which allows to store an information on the end of selection, and the predetermined condition corresponds to writing the Status Bit in the respective memory unit. The selection units are connected in a chain which allows to compute the selection signal for the memory unit of rank i, and two selection signals, direct and inverse, S(i) and SN(i), are transmitted and received by the selection unit of rank i+1. The selection unit is in two embodiments. In the first embodiment, teh selection unit comprises a bistable of type D, an inverter, and three AND gates. In the second embodiment, the selection unit comprises an inverter and a NOR gate. Each memory unit is implemented by a technology of type CMOS, and the fusible elements are constituted by capacitors with thin oxide layers.

公开(公告)号：FR2794895B1

公开(公告)日：2001-09-14

申请号：FR9907429

申请日：1999-06-11

Applicant: ST MICROELECTRONICS SA

Inventor： SCHOELLKOPF JEAN PIERRE

IPC: G11C11/56 ,  H01L21/8246 ,  H01L27/112

Abstract: The read-only memory cell (CM1) has a memory transistor in a semiconductor substrate. The source (S1) is connected to earth, the first metallised line (WL12) to grid (G1) and several auxiliary metallic lines (BL0,BL1,BL2) are connected to the drain (D1) of the transistor.