公开(公告)号：FR2879383A1

公开(公告)日：2006-06-16

申请号：FR0452968

申请日：2004-12-14

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE YVAN ,  TEGLIA YANNICK

IPC: H04L9/06 ,  G06F1/00

Abstract: L'invention concerne un procédé et un circuit de masquage d'un mot numérique (DATAi) par application d'une bijection aléatoire, consistant à appliquer au moins une première opération consistant à sélectionner (31) un sous-ensemble non disjoint dudit mot dont la position et la taille dépendent d'une première quantité aléatoire (K1), et à attribuer (32) à chaque bit du sous-ensemble, l'état du bit de position symétrique par rapport au milieu du sous-ensemble, de façon à obtenir une quantité numérique masquée (MDATAi).

公开(公告)号：FR2850811A1

公开(公告)日：2004-08-06

申请号：FR0301073

申请日：2003-01-30

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE YVAN

IPC: H04L9/06 ,  H04L9/28 ,  G06K19/073

Abstract: The method involves rendering physical traces of an integrated circuit to execute an encryption function of an input data, using a secret quantity (K). The function is executed by masking the input data and unmasking the result of encryption function, by using a random number (R). The masking and unmasking are performed by using two functionally identical operators (OP, OP) that having respective different physical traces. The physical traces on the integrated circuit corresponds to the change in circuit temperature or current consumption. An independent claim is also included for an integrated circuit.

公开(公告)号：DE602006019518D1

公开(公告)日：2011-02-24

申请号：DE602006019518

申请日：2006-04-20

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK ,  POMET ALAIN

IPC: G06F7/72

公开(公告)号：DE602004030863D1

公开(公告)日：2011-02-17

申请号：DE602004030863

申请日：2004-08-27

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK ,  TOMEI AMBROISE

IPC: G06F7/58 ,  G06F1/02

公开(公告)号：DE602005017539D1

公开(公告)日：2009-12-24

申请号：DE602005017539

申请日：2005-06-22

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  TEGLIA YANNICK

IPC: H03K3/84

Abstract: The generator has normalization circuits (3, 4) receiving a bit stream to provide normalized bit streams, and registers (6, 7) storing the normalized bit streams. A detector (8) matches the normalized bit streams and compares the bit streams with one of four possible pairs of bits (00, 01, 10, 11) to increment a value of a counter (9). A block (5) compares the values of the counter to verify equi-distribution of the pairs of bits. An independent claim is also included for a method of detecting a loss of equiprobable character of an output bit stream.

公开(公告)号：DE602004020414D1

公开(公告)日：2009-05-20

申请号：DE602004020414

申请日：2004-02-23

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F21/24 ,  G06K19/073 ,  G06F21/02

Abstract: The device (10) has a non-volatile memory (12) with an initial content after manufacturing and a read only memory (ROM) (14) storing one signature representing the initial content. A calculation unit (16) calculates another signature representing a current content. A control circuit (18) deactivates an operating mode selection signal if the difference between the two signatures is greater than a preset threshold. Independent claims are also included for the following: (A) an integrated circuit having a selection device (B) a method for selecting an operating mode of an integrated circuit having a non-volatile memory programmable after manufacturing.

公开(公告)号：DE60314055D1

公开(公告)日：2007-07-12

申请号：DE60314055

申请日：2003-07-02

Applicant: ST MICROELECTRONICS SA

Inventor： LIARDET PIERRE-YVAN ,  ROMAIN FABRICE ,  TEGLIA YANNICK ,  SIRTORI LAURENCE

IPC: H04L9/06

公开(公告)号：FR2888370A1

公开(公告)日：2007-01-12

申请号：FR0552047

申请日：2005-07-05

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE YVAN ,  POMET ALAIN

IPC: G06K19/073 ,  G06F12/14 ,  G06F21/75 ,  G06F21/77

Abstract: L'invention concerne un procédé de protection de l'exécution d'un programme principal (Pg) contre d'éventuels déroutements, comporte les étapes de, lors d'une instruction du programme principal, déclencher un compteur temporel (TIMER) d'un compte donné en fonction d'instructions qui suivent du programme principal, et exécuter une fois que le compteur a atteint son compte au moins une instruction d'un programme secondaire dont dépend le résultat du programme principal.

公开(公告)号：DE602004000562T2

公开(公告)日：2007-01-11

申请号：DE602004000562

申请日：2004-07-09

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK ,  LIARDET PIERRE-YVAN

IPC: G06F11/00 ,  G06F1/00 ,  G06F11/07 ,  G06F21/52 ,  G06F21/71

Abstract: A non-volatile memory (22) stores value of the verification of an invariant, and periodically recalculates the value in volatile memory. A circuit (21) holds an invariant in normal operation of the processor (1), and compares with stored invariant to detect loss of invariant and occurrence of disturbance in processor. An independent claim is also included for integrated processor.

公开(公告)号：FR2802669B1

公开(公告)日：2002-02-08

申请号：FR9915796

申请日：1999-12-15

Applicant: ST MICROELECTRONICS SA

Inventor： TEGLIA YANNICK

IPC: G06F12/14 ,  G06F1/00 ,  G06F13/38 ,  G06F21/55 ,  G06F21/62 ,  H04L9/34

Abstract: The secured data transfer operates within a programmable circuit containing a processor, controller (UC), ROM and RAM, with a data bus (DBUS) connecting the memories. N octets of secret data are transferred over the data bus, and the octets are sent in a different order each time the data transfer is made, under control of a random number generator (GA).