11.
    发明专利
    未知

    公开(公告)号:DE602004001293D1

    公开(公告)日:2006-08-03

    申请号:DE602004001293

    申请日:2004-06-25

    Abstract: The number of occurrences of operation during program execution are incremented and memorized, by comparing each operation with pre-established list. Number of occurrences are compared with previously stored ranges assigned to each operation at the end of execution. The ranges are determined by analyzing possible statistics deviations of the number of occurrences with respect to program execution. An independent claim is also included for processor for executing program.

    MASQUAGE DE MOTS BINAIRES TRAITES PAR UN CIRCUIT INTEGRE

    公开(公告)号:FR2879383A1

    公开(公告)日:2006-06-16

    申请号:FR0452968

    申请日:2004-12-14

    Abstract: L'invention concerne un procédé et un circuit de masquage d'un mot numérique (DATAi) par application d'une bijection aléatoire, consistant à appliquer au moins une première opération consistant à sélectionner (31) un sous-ensemble non disjoint dudit mot dont la position et la taille dépendent d'une première quantité aléatoire (K1), et à attribuer (32) à chaque bit du sous-ensemble, l'état du bit de position symétrique par rapport au milieu du sous-ensemble, de façon à obtenir une quantité numérique masquée (MDATAi).

    16.
    发明专利
    未知

    公开(公告)号:DE602005017539D1

    公开(公告)日:2009-12-24

    申请号:DE602005017539

    申请日:2005-06-22

    Abstract: The generator has normalization circuits (3, 4) receiving a bit stream to provide normalized bit streams, and registers (6, 7) storing the normalized bit streams. A detector (8) matches the normalized bit streams and compares the bit streams with one of four possible pairs of bits (00, 01, 10, 11) to increment a value of a counter (9). A block (5) compares the values of the counter to verify equi-distribution of the pairs of bits. An independent claim is also included for a method of detecting a loss of equiprobable character of an output bit stream.

    17.
    发明专利
    未知

    公开(公告)号:DE602004020414D1

    公开(公告)日:2009-05-20

    申请号:DE602004020414

    申请日:2004-02-23

    Inventor: TEGLIA YANNICK

    Abstract: The device (10) has a non-volatile memory (12) with an initial content after manufacturing and a read only memory (ROM) (14) storing one signature representing the initial content. A calculation unit (16) calculates another signature representing a current content. A control circuit (18) deactivates an operating mode selection signal if the difference between the two signatures is greater than a preset threshold. Independent claims are also included for the following: (A) an integrated circuit having a selection device (B) a method for selecting an operating mode of an integrated circuit having a non-volatile memory programmable after manufacturing.

    PROTECTION DE L'EXECUTION D'UN PROGRAMME

    公开(公告)号:FR2888370A1

    公开(公告)日:2007-01-12

    申请号:FR0552047

    申请日:2005-07-05

    Abstract: L'invention concerne un procédé de protection de l'exécution d'un programme principal (Pg) contre d'éventuels déroutements, comporte les étapes de, lors d'une instruction du programme principal, déclencher un compteur temporel (TIMER) d'un compte donné en fonction d'instructions qui suivent du programme principal, et exécuter une fois que le compteur a atteint son compte au moins une instruction d'un programme secondaire dont dépend le résultat du programme principal.

    20.
    发明专利
    未知

    公开(公告)号:DE602004000562T2

    公开(公告)日:2007-01-11

    申请号:DE602004000562

    申请日:2004-07-09

    Abstract: A non-volatile memory (22) stores value of the verification of an invariant, and periodically recalculates the value in volatile memory. A circuit (21) holds an invariant in normal operation of the processor (1), and compares with stored invariant to detect loss of invariant and occurrence of disturbance in processor. An independent claim is also included for integrated processor.

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