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18 records (took 0.023 seconds)

    11.
    发明专利
    未知

    公开(公告)号：DE69531823T2

    公开(公告)日：2004-07-01

    申请号：DE69531823

    申请日：1995-07-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  BARCELLA ANTONIO ,  FONTANA MARCO

    IPC: G06F11/20 ,  G11C7/20 ,  H03K3/356 ,  G11C16/06

    Abstract: A latch circuit (1) that is intentionally imbalanced, so that a first output (6) reaches ground voltage and a second output (7) reaches a supply voltage; and a fully static low-consumption fuse circuit the particularity whereof resides in that it comprises the intentionally unbalanced latch circuit (1) and a reversing branch that comprises the fuse to be programmed (6) and is adapted to reverse the operation of the latch circuit, so that in the virgin state the fuse (9) connects the second output (7) of the latch circuit (1) to the ground voltage and connects the first output (6) to the supply voltage.

    12.
    发明专利
    未知

    公开(公告)号：DE69625582T2

    公开(公告)日：2003-11-20

    申请号：DE69625582

    申请日：1996-03-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO

    IPC: G11C7/10 ,  G11C7/00

    Abstract: A non-volatile memory device (1) having optimized management of data transmission lines, having the particularity that it comprises at least one bidirectional internal bus (3) that runs from one end of the memory device to the other, one or more source structures (5', 5'') that lie externally and internally to the memory device (1), and timer means (8); the timer means (8) are adapted to time-control the independent and exclusive access of the external and internal source structures (5', 5''), within a same memory cycle, to the internal bus (3) for the transmission of data, controls, and functions, from one end of the memory (1) to the other over the internal bus (3).

    15.
    发明专利
    未知

    公开(公告)号：DE69721724D1

    公开(公告)日：2003-06-12

    申请号：DE69721724

    申请日：1997-02-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： FONTANA MARCO ,  BARCELLA ANTONIO

    IPC: G11C8/08 ,  G11C16/12 ,  G11C16/06 ,  G11C8/00

    Abstract: In a first operation mode the level shifter (36) transmits as output a logic input signal (Si) and in a second operation mode it shifts the high logic level of the input signal from a low (Vdd) to a high voltage (Vpp). The level shifter comprises a CMOS switch (42) and a pull-up transistor (43); the CMOS switch (42) comprises an NMOS transistor (45) and a PMOS transistor (44) which are connected in parallel between the input (37) and the output (39) of the shifter and have respective control terminals connected to a first supply line (4) at low voltage (Vdd) and, respectively, to a control line (46) connected to ground in the first operation mode and to the high voltage (Vpp) in the second operation mode; the pull-up transistor (43) is connected between the output (39) of the shifter and a second supply line (2) switchable between the low voltage and the high voltage and has a control terminal connected to the first supply line (4).

    16.
    发明专利
    未知

    公开(公告)号：DE69625582D1

    公开(公告)日：2003-02-06

    申请号：DE69625582

    申请日：1996-03-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  BARCELLA ANTONIO

    IPC: G11C7/10 ,  G11C7/00

    Abstract: A non-volatile memory device (1) having optimized management of data transmission lines, having the particularity that it comprises at least one bidirectional internal bus (3) that runs from one end of the memory device to the other, one or more source structures (5', 5'') that lie externally and internally to the memory device (1), and timer means (8); the timer means (8) are adapted to time-control the independent and exclusive access of the external and internal source structures (5', 5''), within a same memory cycle, to the internal bus (3) for the transmission of data, controls, and functions, from one end of the memory (1) to the other over the internal bus (3).

    17.
    发明专利
    未知

    公开(公告)号：DE69625327D1

    公开(公告)日：2003-01-23

    申请号：DE69625327

    申请日：1996-03-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASCUCCI LUIGI ,  ROLANDI PAOLO ,  FONTANA MARCO ,  BARCELLA ANTONIO

    IPC: G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C7/00

    Abstract: A non-volatile memory device, having the particularity that it comprises an internal bus (3) for the transmission of data and other information of the memory to output pads (4); timer means (8); and means (5, 5') for enabling/disabling access to the internal bus; the timer means (8) time the internal bus to transmit information signals of the memory device that originate from local auxiliary lines (7) over the internal bus (3) when the bus is in an inactive period during a normal memory data reading cycle; the timer means (8) drive the enabling/disabling means (5, 5') to allow/deny access to the internal bus (3) on the part of the information signals or of the data from or to the memory.

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