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    11.
    发明专利
    未知

    公开(公告)号：IT1318145B1

    公开(公告)日：2003-07-23

    申请号：ITMI20001567

    申请日：2000-07-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BEZ ROBERTO ,  CAMERLENGHI EMILIO ,  RATTI STEFANO

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

    12.
    发明专利
    未知

    公开(公告)号：ITMI20001567A1

    公开(公告)日：2002-01-11

    申请号：ITMI20001567

    申请日：2000-07-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMERLENGHI EMILIO ,  BEZ ROBERTO ,  RATTI STEFANO

    IPC: H01L21/8247 ,  H01L27/115

    Abstract: A process for fabricating non-volatile memory cells on a semiconductor substrate comprises the following steps: forming a stack structure comprised of a first polysilicon layer (3) isolated from the substrate by an oxide layer (2); cascade etching the first polysilicon layer (3), oxide layer (2), and semiconductor substrate (1) to define a first portion of a floating gate region of the cell and at least one trench (6) bordering an active area (AA) of the memory cell; filling the at least one trench (6) with an isolation layer (7); depositing a second polysilicon layer (8) onto the whole exposed surface of the semiconductor; and etching away the second polysilicon layer (8) to expose the floating gate region formed in the first polysilicon layer (3), thereby forming extensions (9) adjacent to the above portion of the first polysilicon layer (3).

    15.
    发明专利
    未知

    公开(公告)号：DE602005011111D1

    公开(公告)日：2009-01-02

    申请号：DE602005011111

    申请日：2005-06-03

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PELLIZZER FABIO ,  BEZ ROBERTO ,  VARESI ENRICO ,  PIROVANO AGOSTINO ,  PETRUZZA PIETRO

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A process for manufacturing phase change memory cells includes the step of forming a heater element (25a) in a semiconductor wafer (10) and a storage region (31a) of a phase change material on and in contact with the heater element (25a). In order to form the heater element (25a) and the phase change storage region (31a) a heater structure is first formed and a phase change layer (31) is deposited on and in contact with the heater structure. Then, the phase change layer (31) and the heater structure are defined by subsequent self-aligned etch steps.

    16.
    发明专利
    未知

    公开(公告)号：DE60217120D1

    公开(公告)日：2007-02-08

    申请号：DE60217120

    申请日：2002-10-08

    Applicant: ST MICROELECTRONICS SRL ,  OVONYX INC

    Inventor： PELLIZZER FABIO ,  CASAGRANDE GIULIO ,  BEZ ROBERTO

    IPC: H01L27/10 ,  H01L27/24 ,  H01L29/68 ,  H01L45/00

    Abstract: The cell array includes number of N-type base regions (12) which are provided overlying a P-type common collector region (11) in a body (10). P-type emitter regions (14) and N-type base contact regions (15) are formed in the base regions such that the base contact regions have a doping level higher than the doping level of the base regions and each base regions is shared by at least two bipolar transistors (20). An independent claim is also included for a cell array manufacturing process.

    20.
    发明专利
    未知

    公开(公告)号：DE602006012793D1

    公开(公告)日：2010-04-22

    申请号：DE602006012793

    申请日：2006-01-20

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PELLIZZER FABIO ,  TORTORELLI INNOCENZO ,  PIROVANO AGOSTINO ,  BEZ ROBERTO

    IPC: G11C17/16 ,  H01L23/525 ,  H01L27/24

    Abstract: Described herein is a fuse device (1) having a fuse element (2) provided with a first terminal (10) and a second terminal (16) and an electrically breakable region (15a), which is arranged between the first terminal (10) and the second terminal (16) and is configured to undergo breaking as a result of the supply of a programming electrical quantity, thus electrically separating the first terminal (10) from the second terminal (16). The electrically breakable region (15a) is of a phase-change material, in particular a calcogenic material, for example GST.

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