公开(公告)号：ITVA980027A1

公开(公告)日：2000-06-16

申请号：ITVA980027

申请日：1998-12-16

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  CAPODIVACCA GIOVANNI

IPC: H03F1/30

Abstract: The anti-pop circuit includes a unity gain buffer with an input coupled to the source of the reference voltage and an output coupled to the input of the amplifier to accelerate the charging of the input coupling capacitor of the amplifier at every turn-on. The capacitor-charging buffer is automatically disabled before the turning-on of the amplifier. The charging buffer may be enabled at start up by generating an impulse of a pre-established duration at the turn-on instant by a monostable circuit or by disabling it upon verifying the decaying to zero of the charging of current of the input coupling capacitor. The circuit eliminates the popping noise at the turn-on without an excessive delay of the turning-on of the amplifier.

公开(公告)号：DE60039101D1

公开(公告)日：2008-07-17

申请号：DE60039101

申请日：2000-03-31

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  CLERIS MAURO

IPC: H03K4/06 ,  H03K4/02

Abstract: An integrated circuit for producing a small slope voltage ramp (VOUT) is constituted by a circuit generating a periodic triangular current signal (IGM1), a circuit generating, at the beginning of each period of the triangular signal, a pulse (V) of a certain duration ( tau ) much smaller than the period (T) of the triangular signal, a loop input at a node (B) with the triangular current signal and producing on the output node the desired slow voltage ramp (VOUT). The loop comprises a first hold circuit (C2, BUFFER2) coupled to the input node (B) by way of a first switch (SW2) controlled by the pulse (V), a transconductance operational amplifier (OTA1), whose inputs are respectively coupled to the input node (B) and to the output node (VOUT), a second hold circuit (C1, BUFFER1) coupled to the output of the operational transconductance amplifier (OTA1) by way of a second switch (SW1) controlled in a complementary manner respect to the first switch (SW2), and a resistor (R) of a much smaller value than the ratio between the period (T) of the triangular signal and the capacitance of the storage capacitor (C2) of the first hold circuit, connected between the output of the second hold circuit and the input node (B).

公开(公告)号：DE60317806D1

公开(公告)日：2008-01-10

申请号：DE60317806

申请日：2003-12-23

Applicant: ST MICROELECTRONICS SRL

Inventor： CHELLI FABIO ,  BRAMBILLA DAVIDE

IPC: H03F3/68 ,  H03F1/02 ,  H03F1/32 ,  H03F3/30 ,  H03F3/45

Abstract: A method of preventing abrupt voltage changes at the outputs of a pair of amplifiers and a common mode control circuit of a pair of amplifiers that reduce EMI and increased distortions occur when the correlation between the signals that are fed to the four channels of the audio system diminishes has been found. This result is attained by properly generating for each amplifier a reference potential as a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration. This method is implemented in a common mode control circuit for a pair of amplifiers self-configuring in a bridge configuration for driving a first load and in a single-ended mode of operation of one of the amplifiers for driving the first load, in function of the level of a differential input signal, comprising for at least one of the pair of amplifiers a common mode feedback differential amplifier, a storage capacitor connected between any one of the two inputs of the feedback amplifier and a node at a reference potential, by providing the common mode control circuit of means for generating this reference potential.

公开(公告)号：DE60030543D1

公开(公告)日：2006-10-19

申请号：DE60030543

申请日：2000-06-13

Applicant: ST MICROELECTRONICS SRL

Inventor： BRAMBILLA DAVIDE ,  NEBULONI DANIELA ,  CLERIS MAURO

IPC: H03F1/34 ,  H03F1/32

Abstract: The amplifier (1, 2) has an input (2a); an output (2c) supplying an output signal (Vo), and a feedback network (5) connected between the input (2a) and the output (2c), and a distortion detection circuit (1). The feedback network (5; 55) includes a first and a second feedback element (6, 7) arranged in series and forming an intermediate node (10) supplying an intermediate signal (VB) in phase with the output signal (Vo) in absence of distortion, and in phase-opposition with the output signal in presence of distortion. The distortion detection circuit (1) includes a phase-comparating circuit (12, 15) which detects the phase of the output signal (Vo) and of the intermediate signal (VB), and generates a distortion-indicative signal (VCD), when the intermediate signal (VB) is in phase opposition with respect to the output signal (Vo).

公开(公告)号：DE69922961T2

公开(公告)日：2005-12-22

申请号：DE69922961

申请日：1999-10-15

Applicant: ST MICROELECTRONICS SRL

Inventor： RANIERI DANILO ,  BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  CELANT LUCA

IPC: G01R31/316 ,  G01R19/165 ,  G01R31/28 ,  H03F1/52 ,  H04R3/00

Abstract: A method of assessing the offset on the output nodes of an amplifying channel by generating a logic signal signalling the existence of an offset of a level exceeding a window of permitted levels symmetric about the zero level, defined by a negative limit value and by a positive limit value, consists in establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency; sensing the rising edge of the timing pulse and setting a bistable circuit; comparing the signal on the output nodes of the amplifiers channel with said window of permitted values; resetting said bistable circuit upon the occurrence, after said initial setting, of an output signal amplitude within said window of permitted values; failure of said bistable circuit to reset before the end of the detection phase signalling an excessive offset.

公开(公告)号：DE69922961D1

公开(公告)日：2005-02-03

申请号：DE69922961

申请日：1999-10-15

Applicant: ST MICROELECTRONICS SRL

Inventor： RANIERI DANILO ,  BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  CELANT LUCA

IPC: G01R31/316 ,  G01R19/165 ,  G01R31/28 ,  H03F1/52 ,  H04R3/00

Abstract: A method of assessing the offset on the output nodes of an amplifying channel by generating a logic signal signalling the existence of an offset of a level exceeding a window of permitted levels symmetric about the zero level, defined by a negative limit value and by a positive limit value, consists in establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency; sensing the rising edge of the timing pulse and setting a bistable circuit; comparing the signal on the output nodes of the amplifiers channel with said window of permitted values; resetting said bistable circuit upon the occurrence, after said initial setting, of an output signal amplitude within said window of permitted values; failure of said bistable circuit to reset before the end of the detection phase signalling an excessive offset.