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公开(公告)号：JP2001169383A
公开(公告)日：2001-06-22
申请号：JP2000314791
申请日：2000-10-16
Applicant: ST MICROELECTRONICS SRL
Inventor： RANIERI DANILO , BRAMBILLA DAVIDE , BOTTI EDOARDO , CELANT LUCA
IPC: G01R31/316 , G01R19/165 , G01R31/28 , H03F1/52 , H04R3/00
Abstract: PROBLEM TO BE SOLVED: To provide an audio amplifier where occurrence of an unrecoverable damage to a speaker can be avoided. SOLUTION: A detection interval or phase is established by applying a timing pulse with a frequency to an input of the detection circuit of this invention. The detection circuit detects a rising edge of the timing pulse to set a bistable circuit. A signal on an output node of an amplifier channel is compared with a window denoting a permissible value. After the initialization set, the bistable circuit is reset on the basis of production of a level of an output signal in the window denoting the permissible value. When the bistable circuit cannot be reset before the end of the detection phase, the detection circuit informs a user about the presence of an excessive offset.
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公开(公告)号：DE69902889D1
公开(公告)日：2002-10-17
申请号：DE69902889
申请日：1999-06-15
Applicant: ST MICROELECTRONICS SRL
Inventor： BRAMBILLA DAVIDE , CAPODIVACCA GIOVANNI , RANIERI DANILO
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Patent Agency Ranking
公开(公告)号：ITVA990003A1
公开(公告)日：2000-07-19
申请号：ITVA990003
申请日：1999-01-19
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , RANIERI DANILO
Abstract: A switching output power stage, including a power switching device for the supply line and a complementary power switching device for the ground rail driven in phase opposition by a pulse width modulated (PWM) drive signal, is provided with sensors detecting a substantial turn-off state of each of the two power switching devices and generating a pair of logic signals. A combinatory logic circuit combines the drive signal and the pair of logic signals and generates a pair of driving signals of opposite phase for the respective power switching devices. The switching to a turn-on state of any of the two power devices is enabled upon verifying a substantially attained turn-off state by the device complementary to the device commanded to turn-on, irrespective of the process spread and of changes of temperature load conditions and of configuration of a plurality of output stages of a multichannel amplifier.
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公开(公告)号：ITVA990003D0
公开(公告)日：1999-01-19
申请号：ITVA990003
申请日：1999-01-19
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , RANIERI DANILO
Abstract: A switching output power stage, including a power switching device for the supply line and a complementary power switching device for the ground rail driven in phase opposition by a pulse width modulated (PWM) drive signal, is provided with sensors detecting a substantial turn-off state of each of the two power switching devices and generating a pair of logic signals. A combinatory logic circuit combines the drive signal and the pair of logic signals and generates a pair of driving signals of opposite phase for the respective power switching devices. The switching to a turn-on state of any of the two power devices is enabled upon verifying a substantially attained turn-off state by the device complementary to the device commanded to turn-on, irrespective of the process spread and of changes of temperature load conditions and of configuration of a plurality of output stages of a multichannel amplifier.
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公开(公告)号：DE69922961T2
公开(公告)日：2005-12-22
申请号：DE69922961
申请日：1999-10-15
Applicant: ST MICROELECTRONICS SRL
Inventor： RANIERI DANILO , BRAMBILLA DAVIDE , BOTTI EDOARDO , CELANT LUCA
IPC: G01R31/316 , G01R19/165 , G01R31/28 , H03F1/52 , H04R3/00
Abstract: A method of assessing the offset on the output nodes of an amplifying channel by generating a logic signal signalling the existence of an offset of a level exceeding a window of permitted levels symmetric about the zero level, defined by a negative limit value and by a positive limit value, consists in establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency; sensing the rising edge of the timing pulse and setting a bistable circuit; comparing the signal on the output nodes of the amplifiers channel with said window of permitted values; resetting said bistable circuit upon the occurrence, after said initial setting, of an output signal amplitude within said window of permitted values; failure of said bistable circuit to reset before the end of the detection phase signalling an excessive offset.
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公开(公告)号：DE69922961D1
公开(公告)日：2005-02-03
申请号：DE69922961
申请日：1999-10-15
Applicant: ST MICROELECTRONICS SRL
Inventor： RANIERI DANILO , BRAMBILLA DAVIDE , BOTTI EDOARDO , CELANT LUCA
IPC: G01R31/316 , G01R19/165 , G01R31/28 , H03F1/52 , H04R3/00
Abstract: A method of assessing the offset on the output nodes of an amplifying channel by generating a logic signal signalling the existence of an offset of a level exceeding a window of permitted levels symmetric about the zero level, defined by a negative limit value and by a positive limit value, consists in establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency; sensing the rising edge of the timing pulse and setting a bistable circuit; comparing the signal on the output nodes of the amplifiers channel with said window of permitted values; resetting said bistable circuit upon the occurrence, after said initial setting, of an output signal amplitude within said window of permitted values; failure of said bistable circuit to reset before the end of the detection phase signalling an excessive offset.
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公开(公告)号：IT1313380B1
公开(公告)日：2002-07-23
申请号：ITVA990003
申请日：1999-01-19
Applicant: ST MICROELECTRONICS SRL
Inventor： BOTTI EDOARDO , RANIERI DANILO
Abstract: A switching output power stage, including a power switching device for the supply line and a complementary power switching device for the ground rail driven in phase opposition by a pulse width modulated (PWM) drive signal, is provided with sensors detecting a substantial turn-off state of each of the two power switching devices and generating a pair of logic signals. A combinatory logic circuit combines the drive signal and the pair of logic signals and generates a pair of driving signals of opposite phase for the respective power switching devices. The switching to a turn-on state of any of the two power devices is enabled upon verifying a substantially attained turn-off state by the device complementary to the device commanded to turn-on, irrespective of the process spread and of changes of temperature load conditions and of configuration of a plurality of output stages of a multichannel amplifier.
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