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    CONTROLLABLE FREQUENCY OSCILLATOR
    1.
    发明专利
    CONTROLLABLE FREQUENCY OSCILLATOR 失效

    公开(公告)号：JPH1174765A

    公开(公告)日：1999-03-16

    申请号：JP17473498

    申请日：1998-06-22

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CELANT LUCA ,  DEMICHELI MARCO ,  BRUCCOLERI MELCHIORRE ,  RIGAZIO LUCA

    IPC: H03K3/0231 ,  H03K3/282

    Abstract: PROBLEM TO BE SOLVED: To operate with power supply voltage that is lower than normal power supply voltage by configuring a connection circuit means with a differential amplifier which has a differential output terminal that is connected to the bases of two transistors respectively. SOLUTION: A balanced differential amplifier is provided between two transistors Q1 and Q2 as a connecting means for positive feedback. The differential amplifier has two npn transistors T3 and T4, interconnects their emitters, also connects its current Ip to a ground terminal through a current source G5 which is adjusted by the voltage of a control terminal SW, connects their collectors to a power supply terminal Vcc through respectively different resistance R3 and R4 and connects their bases to the collectors of the transistors Q2 and Q1 respectively. The collectors of the transistors T3 and T4 are further connected to bases of the transistors Q2 and Q1 respectively and also each collector can be taken out as an output terminal Vout of this oscillator.

    METHOD AND CIRCUIT FOR DETECTING ABNORMAL OFFSET
    2.
    发明专利
    METHOD AND CIRCUIT FOR DETECTING ABNORMAL OFFSET 失效

    公开(公告)号：JP2001169383A

    公开(公告)日：2001-06-22

    申请号：JP2000314791

    申请日：2000-10-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RANIERI DANILO ,  BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  CELANT LUCA

    IPC: G01R31/316 ,  G01R19/165 ,  G01R31/28 ,  H03F1/52 ,  H04R3/00

    Abstract: PROBLEM TO BE SOLVED: To provide an audio amplifier where occurrence of an unrecoverable damage to a speaker can be avoided. SOLUTION: A detection interval or phase is established by applying a timing pulse with a frequency to an input of the detection circuit of this invention. The detection circuit detects a rising edge of the timing pulse to set a bistable circuit. A signal on an output node of an amplifier channel is compared with a window denoting a permissible value. After the initialization set, the bistable circuit is reset on the basis of production of a level of an output signal in the window denoting the permissible value. When the bistable circuit cannot be reset before the end of the detection phase, the detection circuit informs a user about the presence of an excessive offset.

    INTEGRATED CIRCUIT
    3.
    发明专利
    INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH1186459A

    公开(公告)日：1999-03-30

    申请号：JP19573198

    申请日：1998-07-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CELANT LUCA ,  DE MICHELI MARCO ,  BRUCCOLERI MELCHIORRE ,  RIGAZIO LUCA

    IPC: G11B20/14 ,  H03B29/00 ,  H03L7/07 ,  H03L7/22

    Abstract: PROBLEM TO BE SOLVED: To prevent locking caused by injection of two oscillators due to stray current in an integrated circuit. SOLUTION: The integrated circuit has two phase lock groups, R-PLL, W-PLL, and each of these phase lock groups has its own oscillators OSC-1, OSC-2. The oscillator OSC-2 of one of these phase lock groups, W-PLL, is coupled with a noise generator N-GEN. And a means TM which operates this noise generator N-GEN is installed so that injected noise randomly changes the frequency of the oscillator OSC-2 of the above one phase lock group when the other phase lock group is in operation.

    7.
    发明专利
    未知

    公开(公告)号：DE69922961T2

    公开(公告)日：2005-12-22

    申请号：DE69922961

    申请日：1999-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RANIERI DANILO ,  BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  CELANT LUCA

    IPC: G01R31/316 ,  G01R19/165 ,  G01R31/28 ,  H03F1/52 ,  H04R3/00

    Abstract: A method of assessing the offset on the output nodes of an amplifying channel by generating a logic signal signalling the existence of an offset of a level exceeding a window of permitted levels symmetric about the zero level, defined by a negative limit value and by a positive limit value, consists in establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency; sensing the rising edge of the timing pulse and setting a bistable circuit; comparing the signal on the output nodes of the amplifiers channel with said window of permitted values; resetting said bistable circuit upon the occurrence, after said initial setting, of an output signal amplitude within said window of permitted values; failure of said bistable circuit to reset before the end of the detection phase signalling an excessive offset.

    8.
    发明专利
    未知

    公开(公告)号：DE69922961D1

    公开(公告)日：2005-02-03

    申请号：DE69922961

    申请日：1999-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： RANIERI DANILO ,  BRAMBILLA DAVIDE ,  BOTTI EDOARDO ,  CELANT LUCA

    IPC: G01R31/316 ,  G01R19/165 ,  G01R31/28 ,  H03F1/52 ,  H04R3/00

    Abstract: A method of assessing the offset on the output nodes of an amplifying channel by generating a logic signal signalling the existence of an offset of a level exceeding a window of permitted levels symmetric about the zero level, defined by a negative limit value and by a positive limit value, consists in establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency; sensing the rising edge of the timing pulse and setting a bistable circuit; comparing the signal on the output nodes of the amplifiers channel with said window of permitted values; resetting said bistable circuit upon the occurrence, after said initial setting, of an output signal amplitude within said window of permitted values; failure of said bistable circuit to reset before the end of the detection phase signalling an excessive offset.

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