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11.发明专利
公开(公告)号：JP2002260395A
公开(公告)日：2002-09-13
申请号：JP2002006591
申请日：2002-01-15
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MICHELONI RINO
Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit which is operated appropriately only when a cell current exists though it is minute and which reads out a multi- level memory cell. SOLUTION: A method for reading out a memory cell is based on time integration of current supplied to a memory cell by a capacitive element. The capacitive element is charged first, after that, linear-discharged within a time previously set. During this period, the memory cell is in a biased state by a fixed voltage. In a first operation mode, a first capacitor (22) and a second capacitor (23) are charged respectively to a first charge value and a second charge value first. The second capacitor is discharged with a fixed current within a time previously decided through the memory cell. The first charge value is divided by the first capacitor and the second capacitor, after that, divided electric charges are measured.
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公开(公告)号：JP2001035178A
公开(公告)日：2001-02-09
申请号：JP2000171999
申请日：2000-06-05
Applicant: ST MICROELECTRONICS SRL , MITSUBISHI ELECTRIC CORP
Inventor： MICHELONI RINO , CAMPARDO GIOVANNI , OBA ATSUSHI , CARRERA MARCELLO
IPC: G11C16/06 , G11C5/14 , G11C8/10 , G11C11/56 , G11C16/02 , G11C16/08 , H03K19/00 , H03K19/017 , H03K19/0185 , H03K19/0948
Abstract: PROBLEM TO BE SOLVED: To transfer high voltage to a load or a circuit of a post stage by reducing current loss during switching operation when an input signal of low voltage exists in a switch circuit of a CMOS type for transferring high voltage. SOLUTION: This circuit is provided with first, second and third reference potential lines 50, 54, 55, a control input 41a receiving a control signal being swithable between the first and the third potentials, and a drive inverter stage 44 having an input node and an output node 70, a feedback inverter stage 43 is provided with a first upper part transistor and a lower part transistor 51, 53, a control terminal of the first upper part transistor is connected to an output node, a control terminal of the first lower part transistor is connected to a control input, an intermediate node 58 of the feedback inverter stage is connected to an input node, start elements 80, 71 facilitate switching of the intermediate node from a third potential to a second potential.
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13.发明专利
公开(公告)号：JP2000251480A
公开(公告)日：2000-09-14
申请号：JP2000049429
申请日：2000-02-25
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , CAMPARDO GIOVANNI
Abstract: PROBLEM TO BE SOLVED: To provide a read-out method and a memory by which a multi-level cell can be read out quickly and reliably. SOLUTION: Reading circuits 30, 31, 32 comparing the current flowing in a cell containing plural reference currents are not same mutually, but the compared current is made different and amplified. Especially, the reading circuit 32 relating to the minimum reference current IR3 amplifies a cell current of other reading circuits 30, 31 or more until reaching respective reference current 33c. Thereby, current dynamics is increased, read-out voltage can be kept at a low level. Thus, an intrinsic characteristic of the minimum reference current IR3 is near a characteristic of a memory cell distribution IM3 or in the characteristic, possibility of discrimination among different logic levels is reduced.
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公开(公告)号：JP2000113689A
公开(公告)日：2000-04-21
申请号：JP28002499
申请日：1999-09-30
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MICHELONI RINO
Abstract: PROBLEM TO BE SOLVED: To erase a load charge voltage with a column format memory matrix by comprising a PMOS type first transistor having a conductive terminal in which one is connected to a main word line and the other is connected to a local word line, a NMOS type second transistor having a conductive terminal in which one is connected to a local word line and the other is connected to the reference voltage. SOLUTION: A storage device 1 is connected in the upstream of each local row LWL of a memory matrix within each sector of a non-volatile memory matrix. The storage device 1 includes the PMOS type transistor M1 connected to the conductive terminal between the main word line MWL and local word line LWL and the NMOS type transistor M3 connected to the conductive terminal between the local word line LWL and reference voltage GND. The gate terminals of all transistor M3 of the storage device 1 are all connected together to receive a voltage signal. Thereby, row decoding of the hierarchical structure may be realized.
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15.发明专利
公开(公告)号：JPH11260083A
公开(公告)日：1999-09-24
申请号：JP37435898
申请日：1998-12-28
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , CAMPARDO GIOVANNI , FERRARIO DONATO , GHEZZI STEFANO
IPC: G11C16/06 , G11C8/08 , G11C11/408
Abstract: PROBLEM TO BE SOLVED: To enable accurate operation in different conditions by providing a cascade-connected inverter of a hierarchical structure, a circuit for dynamically increasing step by step a read voltage level, a first means for increasing a read voltage level to a particular voltage and a second means for increasing a read voltage level to the other particular voltage. SOLUTION: A first means increases a read voltage level to a value equal to the supply voltage + threshold voltage and a second means increases a read voltage level to a value equal to the supply voltage +2 × threshold voltage. A memory row is selected by simultaneously setting the pre-decoding signals LX, LY, LZ and P to high logical values to form a first decoding final inverter 15 provided with the transistors M9 and M10. The voltage supplied to the designated rows of address is boosted to Vcc+2Vtp. In the rows not designated, the voltage Vcc+Vtp is transferred to the center node Xc of the transistors M9 and M10.
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Patent Agency Ranking
公开(公告)号：JP2002124093A
公开(公告)日：2002-04-26
申请号：JP2001316940
申请日：2001-10-15
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , CAMPARDO GIOVANNI
Abstract: PROBLEM TO BE SOLVED: To provide a storing method for enabling to increase storage capacitor of a non-volatile memory without pressing excessively requirement of read-out accuracy, complexness, and evaluation for danger. SOLUTION: A data control method is applied to a multiple level non-volatile memory device having a memory array 10 formed by plural memory cells 11. Each of the memory cell 11 stores, for example, plural bits being 3 other than integer power of 2. One data byte is stored in numbers of non-integer in the memory cell 11 in this method. In this control method, data words formed by plural byte are stored in the same clock cycle by programming the number previously decided of the adjacent memory cell 11. Read-out is programmed by reading out a stored data word in the same clock cycle.
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公开(公告)号：JP2001084782A
公开(公告)日：2001-03-30
申请号：JP2000253119
申请日：2000-07-21
Applicant: ST MICROELECTRONICS SRL
Inventor： MICHELONI RINO , CAMPARDO GIOVANNI , CRIPPA LUCA
Abstract: PROBLEM TO BE SOLVED: To eliminate the drawback that reduction of read time is limited at a low supply voltage. SOLUTION: A read circuit 1' comprises an array branch 6 having an input array node 22 connected, via an array bit line 8, to an array cell 10; a reference branch 12 having an input reference node 32 connected, via a reference bit line 14, to a reference cell 16; a current-to-voltage converter 18 connected to an output array node 56 of the array branch and to an output reference node of the reference branch to supply on both nodes 56, 58 the respective electric potentials VM, VR correlated to the currents flowing in both cells 10, 16; and a comparator 19 connected at input to both nodes 56, 58 and supplying as output a signal OUT indicative of the contents stored in the array memory cell 10; and an array decoupling stage 80 arranged between both array nodes 22, 56 to decouple both array nodes 22, 56 from one another.
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公开(公告)号：JP2000057789A
公开(公告)日：2000-02-25
申请号：JP15223299
申请日：1999-05-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MICHELONI RINO , MAURELLI ALFONSO
Abstract: PROBLEM TO BE SOLVED: To reduce the complexity in the design and control of a reference cell by comparing charge states with each other, and by generating a two-bit signal for coding the charge states by the output. SOLUTION: In the case of both erased memory cells, even when cells F1 and F2 adsorb different current, mirroring is made in first and second current mirror circuits 19, 20, 33, and 34, and voltages 01 and 02 are set to a high level for corresponding to a logic state '11'. In the written cells F1 and F2, the cells do not adsorb current, and current being mirrored in first and second current mirror circuits 19, 20, 22, and 23 is insufficient to reduce the voltage in I/O nodes 41a and 41b. The output voltages 01 and 02 correspond to a logic state '00'. In the case of the cells F1 and F2 being similarly erased and written, respectively, and in the case of the cells F1 and F2 being written and erased, respectively, the each logic state is set to '10' or '01'.
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公开(公告)号：JPH11274319A
公开(公告)日：1999-10-08
申请号：JP37471898
申请日：1998-12-28
Inventor： COLOMBO PAOLO , MULATTI JACOPO , CAMPARDO GIOVANNI , MACCARRONE MARCO , ANNUNZIATA ROBERTO
IPC: H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/092
CPC classification number: H01L27/0259 , H01L27/0251
Abstract: PROBLEM TO BE SOLVED: To provide an electrostatic discharge(ESD) protective network, which has such structural and functional features that meet the nonsensitive requirements of a substrate for noise and accordingly, can isolate various circuit blocks from noise or disturbance. SOLUTION: An ESD protective network incorporates first ESD protective parts 14 for the input stage of a circuit structure, second ESD protective parts 5 for the output stage of the circuit structure, at least one ESD protective parts B0 between a primary power source Vcc and a primary ground GND, and at least one EDGE protective parts B between a secondary power source Vcc- IO and a secondary ground GND- IO, and the first and second protective parts 15 and 5 commonly use the input-output terminal 20 of an integrated circuit structure.
Abstract translation: 要解决的问题：提供一种静电放电（ESD）保护网络，其具有满足基板对噪声的不敏感要求的结构和功能特征，因此可以将各种电路块与噪声或干扰隔离开来。 解决方案：ESD保护网络包括用于电路结构的输入级的第一ESD保护部件14，用于电路结构的输出级的第二ESD保护部件5，主电源Vcc和 主接地GND以及次级电源Vcc-IO和次级地GND-IO之间的至少一个EDGE保护部分B，并且第一和第二保护部分15和5通常使用集成电路的输入 - 输出端子20 结构体。
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20.发明专利
公开(公告)号：JPH11232883A
公开(公告)日：1999-08-27
申请号：JP33595098
申请日：1998-11-26
Applicant: ST MICROELECTRONICS SRL
Inventor： CAMPARDO GIOVANNI , MICHELONI RINO
Abstract: PROBLEM TO BE SOLVED: To provide a row decoder which can erase selectively one or plural rows of some sector of a memory array of a flash memory device. SOLUTION: A row decoder has plural pre-decoding circuits generating pre- decoding signals and plural final decoding circuits driving each row of arrays, and each pre-decoding circuit has a push-pull output and four parallel paths for signal. A first path 50 drives a pull-up transistor when read-out is performed under low voltage, and a second path 52 drives a pull-up transistor when programming and erasing are performed under positive high voltage. A third path drives a pull-down transistor when read-out and programming are performed under low voltage, and a fourth path drives a pull-down transistor when erasing are performed under negative high voltage. There are two selections that one of the first and the second paths 50, 52 and one of the third and the fourth paths are used in accordance with an operation step.
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