公开(公告)号：DE69326749D1

公开(公告)日：1999-11-18

申请号：DE69326749

申请日：1993-02-17

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE

IPC: G11C5/00 ,  H01L21/8247 ,  H01L27/02 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

公开(公告)号：FR3084961B1

公开(公告)日：2021-12-10

申请号：FR1857390

申请日：2018-08-08

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  NAVARRO GABRIELE

IPC: H01L21/8256 ,  H01L21/8258

Abstract: La présente description concerne une cellule mémoire à changement de phase (100) comprenant un empilement d'au moins une couche (114) de germanium recouverte d'une couche (116) d'un premier alliage à base de germanium, d'antimoine et de tellure.

公开(公告)号：DE69325767D1

公开(公告)日：1999-09-02

申请号：DE69325767

申请日：1993-04-01

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  RAVAZZI LEONARDO

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/66

公开(公告)号：DE69313816T2

公开(公告)日：1998-03-26

申请号：DE69313816

申请日：1993-02-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  CANTARELLI DANIELE

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

Abstract: A process for simultaneously fabricating a flash-EEPROM memory and circuit transistors using the DPCC process wherein the first polysilicon layer is not removed from the circuit area (40a), and the gate regions of the circuit transistors are formed by shorting first and second polysilicon layers. The thin tunnel oxide layer (61) of the memory cells is formed using the same mask (36) provided for implanting boron (38) into the cell area (40b) of the substrate (38). Following implantation and without removing the mask, the gate oxide (35') formed previously over the whole surface of the wafer is removed from the cell area; the boron implant (38) mask is removed; and tunnel oxidation is performed so as to increase the thickness of the tunnel oxide (61) by the desired amount, and slightly increase the thickness of the oxide (gate oxide 35'') in the transistor area (40a).

公开(公告)号：DE69313816D1

公开(公告)日：1997-10-16

申请号：DE69313816

申请日：1993-02-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  CANTARELLI DANIELE

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

Abstract: A process for simultaneously fabricating a flash-EEPROM memory and circuit transistors using the DPCC process wherein the first polysilicon layer is not removed from the circuit area (40a), and the gate regions of the circuit transistors are formed by shorting first and second polysilicon layers. The thin tunnel oxide layer (61) of the memory cells is formed using the same mask (36) provided for implanting boron (38) into the cell area (40b) of the substrate (38). Following implantation and without removing the mask, the gate oxide (35') formed previously over the whole surface of the wafer is removed from the cell area; the boron implant (38) mask is removed; and tunnel oxidation is performed so as to increase the thickness of the tunnel oxide (61) by the desired amount, and slightly increase the thickness of the oxide (gate oxide 35'') in the transistor area (40a).

公开(公告)号：FR3084961A1

公开(公告)日：2020-02-14

申请号：FR1857390

申请日：2018-08-08

Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  NAVARRO GABRIELE

IPC: H01L21/8256 ,  H01L21/8258

Abstract: La présente description concerne une cellule mémoire à changement de phase (100) comprenant un empilement d'au moins une couche (114) de germanium recouverte d'une couche (116) d'un premier alliage à base de germanium, d'antimoine et de tellure.

公开(公告)号：DE69229673T2

公开(公告)日：1999-12-02

申请号：DE69229673

申请日：1992-10-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  RAVAZZI LEONARDO

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/66

公开(公告)号：DE69229673D1

公开(公告)日：1999-09-02

申请号：DE69229673

申请日：1992-10-29

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  RAVAZZI LEONARDO

IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/66

公开(公告)号：FR3119270A1

公开(公告)日：2022-07-29

申请号：FR2100747

申请日：2021-01-27

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  REDAELLI ANDREA

IPC: H01L45/00 ,  G11C13/00

Abstract: Cellule de commutation La présente description concerne une cellule électronique (100) comprenant un empilement intégré ayant successivement : une première électrode (105) ; une couche de commutateur à seuil ovonique (104) ; et une résistance (102). Figure pour l'abrégé : Fig. 1

公开(公告)号：DE602005019244D1

公开(公告)日：2010-03-25

申请号：DE602005019244

申请日：2005-11-25

Applicant: ST MICROELECTRONICS SRL

Inventor： PELLIZZER FABIO ,  CAPPELLETTI PAOLO GIUSEPPE

IPC: H01L27/07 ,  H01L21/8249 ,  H01L27/24

Abstract: Integrated transistor device (10) formed in a chip of semiconductor material (15) having an electrical-insulation region (31) delimiting an active area (30) accommodating a bipolar transistor (11) of vertical type and a MOSFET (12) of planar type, contiguous to one another. The active area accommodates a collector region (18); a bipolar base region (19) contiguous to the collector region; an emitter region (20) within the bipolar base region; a source region (23), arranged at a distance from the bipolar base region; a drain region (24); a channel region (22) arranged between the source region and the drain region; and a well region (35). The drain region (24) and the bipolar base region (19) are contiguous and form a common base structure (19, 24, 37) shared by the bipolar transistor and the MOSFET. Thereby, the integrated transistor device (10) has a high input impedance and is capable of driving high currents, while only requiring a small integration area.