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    MANUFACTURE OF INTEGRATED CIRCUIT
    1.
    发明专利
    MANUFACTURE OF INTEGRATED CIRCUIT 失效

    公开(公告)号：JP2000164835A

    公开(公告)日：2000-06-16

    申请号：JP33420599

    申请日：1999-11-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  MAURELLI ALFONSO

    IPC: H01L21/8238 ,  H01L21/8247 ,  H01L27/092 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To provide a process that can easily integrate a nonvolatile memory and a high-performance logic circuit on the same chip. SOLUTION: A method for manufacturing integrated circuit includes the steps of forming first gate oxide layers of first transistors on first sections of a substrate 1, a step of forming a second gate oxide layer 5 of memory cells on second sections of the substrate 1, and a step of forming gate electrodes 8 of the first transistors and floating gate electrodes 7 of the memory cells of first polysilicon layers 6 in the first and second gate oxide layers 3 and 5. The method also includes a step of forming dielectric layers o the floating gate electrodes 7, a step of forming third gate oxide layers 24 of second transistors on third sections of the substrate 1, a step of forming control gate electrodes of the memory cells and the gate electrodes of the second transistor of second polysilicon layers on the dielectric layers and third sections of the substrate 1, and a step of forming the source and drain regions of the first transistors on the first sections of the substrate 1. In addition to these steps, the method also includes a step of forming source and drain regions of memory cells on the second sections of the substrate 1 and a step of forming the source and drain region of the second transistors on the third sections of the substrate 1.

    EVALUATING METHOD AND TESTING EQUIPMENT FOR GATE OXIDE LAYER OF NONVOLATILE MEMORY
    3.
    发明专利
    EVALUATING METHOD AND TESTING EQUIPMENT FOR GATE OXIDE LAYER OF NONVOLATILE MEMORY 失效

    公开(公告)号：JPH077140A

    公开(公告)日：1995-01-10

    申请号：JP27248493

    申请日：1993-10-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  RAVAZZI LEONARDO

    IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

    Abstract: PURPOSE: To detect the presence of a defective cell by analyzing current-voltage characteristic by using a test equipment which is the same as a memory array to be evaluated, except when each cell is connected in parallel. CONSTITUTION: In a test equipment 10, to which access can be performed from the outside by single pads 15, 18, and 21, an electric stress is applied to the gate oxide layers of EPROM, EEPROM, and flash EEPROM memories, so that electrons can be extracted from the floating gate region of a deflective cell, and a threshold characteristic of the cell are changed, while the charge of a non-defective cell remains without being charged. Then, a voltage lower than the threshold is applied, and drain currents related to the presence of at least one defective cell in an equipment passing through the cell are measured. The measurement and analysis of the current-voltage characteristic are conducted for deciding the number of defective cells. Gate currents can be measured indirectly through the measurement of the drain and source currents of the cells, and the detection of the defective cells can be attained.

    EVALUATING METHOD OF DIELECTRIC LAYER OF CELL OF NONVOLATILE MEMORY ARRAY AND TESTING DEVICE OF NONVOLATILE MEMORY ARRAY
    5.
    发明专利
    EVALUATING METHOD OF DIELECTRIC LAYER OF CELL OF NONVOLATILE MEMORY ARRAY AND TESTING DEVICE OF NONVOLATILE MEMORY ARRAY 失效

    公开(公告)号：JPH076599A

    公开(公告)日：1995-01-10

    申请号：JP27248593

    申请日：1993-10-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  RAVAZZI LEONARDO

    IPC: G11C17/00 ,  G11C29/00 ,  G11C29/50 ,  G11C29/56 ,  H01L21/66 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

    Abstract: PURPOSE: To easily find the existence of a defective cell by impressing voltage which is lower than normal threshold on a testing device and measuring and analyzing a current-voltage characteristic. CONSTITUTION: A cell drain area of a testing device 10 of a flash EPROM memory, etc., is mutually connected by metallic lines 13, and a metallic source line 17 and control gate lines 19 are mutually connected. The device 10 which can externally access by single pads 15 to 21 is electrically equivalent in entire cells that are connected in parallel. When the device 10 is given stress by extracting electrons from a floating gate consisting of a gate oxide layer cell that has a defect and a method leaving a charged state of the other cells that are not charged as it is, only threshold voltage of the cell having defect is reduced. Therefore, by impressing the voltage which is lower than normal threshold voltage of the device 10, measuring a current-voltage characteristic and analyzing it, a defective is found.

    Cellule mémoire
    7.
    发明专利
    Cellule mémoire 未知

    公开(公告)号：FR3096826B1

    公开(公告)日：2022-06-03

    申请号：FR1905663

    申请日：2019-05-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO GIUSEPPE

    IPC: G11C13/00 ,  H01L45/00

    Abstract: Cellule mémoire La présente description concerne une cellule mémoire à changement de phase (200), comprenant : un élément chauffant (202) ; et une couche cristalline (206), située au-dessus de l’élément chauffant (202), des parois latérales de la cellule (200) étant entourées par une région isolante (212). Figure pour l'abrégé : Fig. 2

    Cellule mémoire
    9.
    发明专利
    Cellule mémoire 未知

    公开(公告)号：FR3096826A1

    公开(公告)日：2020-12-04

    申请号：FR1905663

    申请日：2019-05-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAPPELLETTI PAOLO GIUSEPPE

    IPC: G11C13/00 ,  H01L45/00

    Abstract: Cellule mémoire La présente description concerne une cellule mémoire à changement de phase (200), comprenant : un élément chauffant (202) ; et une couche cristalline (206), située au-dessus de l’élément chauffant (202), des parois latérales de la cellule (200) étant entourées par une région isolante (212). Figure pour l'abrégé : Fig. 2

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