公开(公告)号：JPH077093A

公开(公告)日：1995-01-10

申请号：JP1674494

申请日：1994-02-10

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  CANTARELLI DANIELE

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE: To provide a non-volatile memory cell and a circuit transistor for flash EEPROM at low cost. CONSTITUTION: A 1st polysilicon layer is not removed from a circuit area 40a, a gate region of a circuit transistor is formed by short-circuiting 1st and 2nd polysilicon layers, a thin tunnel oxide layer 61 of a memory cell is formed by using identical mask, a gate oxide layer is removed from a cell area without removing the mask after ion-implantation, and a boron implant mask is removed.

公开(公告)号：DE69630663D1

公开(公告)日：2003-12-18

申请号：DE69630663

申请日：1996-01-24

Applicant: ST MICROELECTRONICS SRL

Inventor： VILLA CORRADO ,  BEZ ROBERTO ,  CANTARELLI DANIELE ,  DALLABORA MARCO

IPC: G11C16/02 ,  G11C16/06 ,  G11C16/14

公开(公告)号：DE69313816T2

公开(公告)日：1998-03-26

申请号：DE69313816

申请日：1993-02-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  CANTARELLI DANIELE

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

Abstract: A process for simultaneously fabricating a flash-EEPROM memory and circuit transistors using the DPCC process wherein the first polysilicon layer is not removed from the circuit area (40a), and the gate regions of the circuit transistors are formed by shorting first and second polysilicon layers. The thin tunnel oxide layer (61) of the memory cells is formed using the same mask (36) provided for implanting boron (38) into the cell area (40b) of the substrate (38). Following implantation and without removing the mask, the gate oxide (35') formed previously over the whole surface of the wafer is removed from the cell area; the boron implant (38) mask is removed; and tunnel oxidation is performed so as to increase the thickness of the tunnel oxide (61) by the desired amount, and slightly increase the thickness of the oxide (gate oxide 35'') in the transistor area (40a).

公开(公告)号：DE69313816D1

公开(公告)日：1997-10-16

申请号：DE69313816

申请日：1993-02-11

Applicant: ST MICROELECTRONICS SRL

Inventor： CAPPELLETTI PAOLO GIUSEPPE ,  CANTARELLI DANIELE

IPC: H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/82

Abstract: A process for simultaneously fabricating a flash-EEPROM memory and circuit transistors using the DPCC process wherein the first polysilicon layer is not removed from the circuit area (40a), and the gate regions of the circuit transistors are formed by shorting first and second polysilicon layers. The thin tunnel oxide layer (61) of the memory cells is formed using the same mask (36) provided for implanting boron (38) into the cell area (40b) of the substrate (38). Following implantation and without removing the mask, the gate oxide (35') formed previously over the whole surface of the wafer is removed from the cell area; the boron implant (38) mask is removed; and tunnel oxidation is performed so as to increase the thickness of the tunnel oxide (61) by the desired amount, and slightly increase the thickness of the oxide (gate oxide 35'') in the transistor area (40a).