EVALUATING METHOD OF DIELECTRIC LAYER OF CELL OF NONVOLATILE MEMORY ARRAY AND TESTING DEVICE OF NONVOLATILE MEMORY ARRAY

    公开(公告)号:JPH076599A

    公开(公告)日:1995-01-10

    申请号:JP27248593

    申请日:1993-10-29

    Abstract: PURPOSE: To easily find the existence of a defective cell by impressing voltage which is lower than normal threshold on a testing device and measuring and analyzing a current-voltage characteristic. CONSTITUTION: A cell drain area of a testing device 10 of a flash EPROM memory, etc., is mutually connected by metallic lines 13, and a metallic source line 17 and control gate lines 19 are mutually connected. The device 10 which can externally access by single pads 15 to 21 is electrically equivalent in entire cells that are connected in parallel. When the device 10 is given stress by extracting electrons from a floating gate consisting of a gate oxide layer cell that has a defect and a method leaving a charged state of the other cells that are not charged as it is, only threshold voltage of the cell having defect is reduced. Therefore, by impressing the voltage which is lower than normal threshold voltage of the device 10, measuring a current-voltage characteristic and analyzing it, a defective is found.

    EVALUATING METHOD AND TESTING EQUIPMENT FOR GATE OXIDE LAYER OF NONVOLATILE MEMORY

    公开(公告)号:JPH077140A

    公开(公告)日:1995-01-10

    申请号:JP27248493

    申请日:1993-10-29

    Abstract: PURPOSE: To detect the presence of a defective cell by analyzing current-voltage characteristic by using a test equipment which is the same as a memory array to be evaluated, except when each cell is connected in parallel. CONSTITUTION: In a test equipment 10, to which access can be performed from the outside by single pads 15, 18, and 21, an electric stress is applied to the gate oxide layers of EPROM, EEPROM, and flash EEPROM memories, so that electrons can be extracted from the floating gate region of a deflective cell, and a threshold characteristic of the cell are changed, while the charge of a non-defective cell remains without being charged. Then, a voltage lower than the threshold is applied, and drain currents related to the presence of at least one defective cell in an equipment passing through the cell are measured. The measurement and analysis of the current-voltage characteristic are conducted for deciding the number of defective cells. Gate currents can be measured indirectly through the measurement of the drain and source currents of the cells, and the detection of the defective cells can be attained.

    10.
    发明专利
    未知

    公开(公告)号:DE69413960T2

    公开(公告)日:1999-04-01

    申请号:DE69413960

    申请日:1994-07-18

    Abstract: A nonvolatile memory (40) having a cell (31) comprising an N type source region (24) and drain region (12) embedded in a P type substrate (4) and surrounded by respective P-pockets (26, 16). The drain and source P-pockets (16, 26) are formed in two different high-angle boron implantation steps designed to optimize implantation energy and dosage for ensuring scalability of the cell and avoiding impairment of the snap-back voltage. The resulting cell (31) also presents a higher breakdown voltage as compared with known cells.

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