公开(公告)号：DE69320630D1

公开(公告)日：1998-10-01

申请号：DE69320630

申请日：1993-09-14

Applicant: ST MICROELECTRONICS SRL

Inventor： BETTI GIORGIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID

IPC: H03F1/30 ,  H03F3/45 ,  H03K5/1536 ,  H03K17/13 ,  H03K17/60

Abstract: The offset of a zero-crossing detector circuit is virtually eliminated by inverting the inputs of the comparator after a certain delay from a detected zero-crossing while storing the output state assumed pursuant the detection of a zero-crossing for an interval of time longer than said delay but shorter than the minimum interval of time occurring between any two successive zero-crossings of the input signal.

公开(公告)号：DE69421072T2

公开(公告)日：2000-04-20

申请号：DE69421072

申请日：1994-05-23

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  PISATI VALERIO

IPC: G11B20/14 ,  G11B5/02 ,  G11B5/09 ,  G11B5/596 ,  G11B20/06 ,  G11B20/10 ,  G11B20/18 ,  G11B21/10

Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).

公开(公告)号：DE69327053T2

公开(公告)日：2000-02-24

申请号：DE69327053

申请日：1993-09-21

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  BETTI GIORGIO ,  ALINI ROBERTO

IPC: G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14

Abstract: In a decoder for decoding a serial data stream, employing an extracted base clock signal, synchronous with an input, coded, serial data stream, a fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary clock signal for synthesizing a pre-decoded value produced by a first combinative logic network within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop, a pipelined operation is implemented by momentarily storing the bits that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock the processing by said first combinative network of the n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the raising front of the outpunt sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating spead may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.

公开(公告)号：DE69421072D1

公开(公告)日：1999-11-11

申请号：DE69421072

申请日：1994-05-23

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  PISATI VALERIO

IPC: G11B20/14 ,  G11B5/02 ,  G11B5/09 ,  G11B5/596 ,  G11B20/06 ,  G11B20/10 ,  G11B20/18 ,  G11B21/10

Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).

公开(公告)号：DE69421071D1

公开(公告)日：1999-11-11

申请号：DE69421071

申请日：1994-05-23

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  ALINI ROBERTO

IPC: G11B5/09 ,  G11B20/10

Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.

公开(公告)号：DE69530838D1

公开(公告)日：2003-06-26

申请号：DE69530838

申请日：1995-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： GADDUCCI PAOLO ,  MOLONEY DAVID ,  BRIANTI FRANCESCO ,  PISATI VALERIO

IPC: G06F7/02

Abstract: The invention relates to a basic cell (11) for comparing a first and a second digital signal (A, B), of the type having at least a first and a second input (I1, I2) and a first and a second output (O3, O4) and comprising at least one logic gate (14) receiving digital signals (A, B) at a first and a second signal input (IS1, IS2), and which comprises at least a first and a second controlled switch (P1, P2) inserted in parallel with each other between the output terminal of the logic gate (14) and the second output (O4) from the cell (11), the first switch (P1) being also connected between the first input (I1) and the first output (O3) of the cell (11) and the second switch (P2) being also connected between the second input (I2) and the second output (O4) of the cell (11). The invention also relates to a digital comparator (9) comprising a plurality of basic cells according to the invention.

公开(公告)号：DE69431656D1

公开(公告)日：2002-12-12

申请号：DE69431656

申请日：1994-08-12

Applicant: ST MICROELECTRONICS SRL

Inventor： BRIANTI FRANCESCO ,  ALINI ROBERTO ,  PISATI VALERIO ,  GADDUCCI PAOLO

IPC: H03H11/04 ,  H03H1/00

Abstract: A high-pass filter in particular for high-frequency applications and of the type comprising at least one input terminal (IN) and at least one output terminal (OUT) between which is defined a transfer function (FdT) and is inserted a biquadratic cell (18) incorporating a series of transconductance stages (2, 3, 4, 5) comprises a generator circuit (29) of variable currents (iK1, iK2) connected between a pair of stages (2, 3) of the biquadratic cell (18) and a voltage reference (GND). Said generator allows introduction of programmable zeroes in the transfer function (FdT) of the filter (20).

公开(公告)号：DE69330957T2

公开(公告)日：2002-04-04

申请号：DE69330957

申请日：1993-11-10

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  DEMICHELI MARCO ,  ALINI ROBERTO

IPC: G06F3/06 ,  G11B20/10 ,  G11B20/14 ,  H03M5/14

公开(公告)号：DE69421071T2

公开(公告)日：2000-04-20

申请号：DE69421071

申请日：1994-05-23

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  ALINI ROBERTO

IPC: G11B5/09 ,  G11B20/10

Abstract: The device comprises a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel sampling channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two sampling channels (24, 34) comprise, each of them, an analog-digital converter (26, 36) and a Viterbi detector (27, 37) arranged in succession one after the other and operating according to sampling sequences that alternate with one another.