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公开(公告)号：JPH1174765A
公开(公告)日：1999-03-16
申请号：JP17473498
申请日：1998-06-22
Applicant: ST MICROELECTRONICS SRL
Inventor： CELANT LUCA , DEMICHELI MARCO , BRUCCOLERI MELCHIORRE , RIGAZIO LUCA
IPC: H03K3/0231 , H03K3/282
Abstract: PROBLEM TO BE SOLVED: To operate with power supply voltage that is lower than normal power supply voltage by configuring a connection circuit means with a differential amplifier which has a differential output terminal that is connected to the bases of two transistors respectively. SOLUTION: A balanced differential amplifier is provided between two transistors Q1 and Q2 as a connecting means for positive feedback. The differential amplifier has two npn transistors T3 and T4, interconnects their emitters, also connects its current Ip to a ground terminal through a current source G5 which is adjusted by the voltage of a control terminal SW, connects their collectors to a power supply terminal Vcc through respectively different resistance R3 and R4 and connects their bases to the collectors of the transistors Q2 and Q1 respectively. The collectors of the transistors T3 and T4 are further connected to bases of the transistors Q2 and Q1 respectively and also each collector can be taken out as an output terminal Vout of this oscillator.
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公开(公告)号：JPH0730336A
公开(公告)日：1995-01-31
申请号：JP5280894
申请日：1994-02-25
Applicant: ST MICROELECTRONICS SRL
Inventor： DEMICHELI MARCO
Abstract: PURPOSE: To attain simple and effective temperature compensation without being influenced by the variation of a processing parameter by providing the converter with a uniform gain non-inverted interface circuit and a bipolar junction circuit element connected to a reference voltage circuit. CONSTITUTION: The combination of differential structures M3, M4 and current mirror structures M5, M6 constitutes an operational amplifier of which inverted input terminal and output terminal are respectively connected to the source and gate terminals of a transistor(TR) M2. The combination of the operational amplifier and the TR M2 can be regarded as a non-inverted interface circuit having uniform gain. Transistors Q1, M1 generate low impedance reference voltage equal to the value of reference voltage VREF and the base-emitter voltage of the Q1 on a point E. When an input current is changed, expotentially functional variation is generated in an output current by the voltage drop of a node B due to a resistor R. In the constitution, a temperature compensating means can be added without being influenced by a processing parameter.
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公开(公告)号：JP2000195169A
公开(公告)日：2000-07-14
申请号：JP35109399
申请日：1999-12-10
Applicant: ST MICROELECTRONICS SRL
Inventor： DEMICHELI MARCO , BRUCCOLERI MELCHIORRE , MALFA MAURIZIO , BOLLATI GIACOMINO
Abstract: PROBLEM TO BE SOLVED: To provide a method and a circuit for pre-compensating interference between marks in a large capacity storage device. SOLUTION: This device supplys a digital data stream (I) and a clock signal (Ck) to be stored in a 1st circuit and also makes the 1st circuit(CC1) output a pair of digital streams (N, R). Further, the digital streams (N, R) and the clock signal (Ck) are supplied to a 2nd circuit (DC1), and the 2nd circuit outputs a digital data stream (O) directed to a write head. In such a case, by sampling the two digital streams (N, R) by a pair of flip-flops (FN2, FR2) and also re- coupling the signals outputted from the pair of flip-flops (FN1, FR2) with a digital data stream (O) via a logical XOR gate (X1), the device delays a transition immediately following a preceding transition by a predetermined time interval (Δwp).
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公开(公告)号：JP2000174626A
公开(公告)日：2000-06-23
申请号：JP33007299
申请日：1999-11-19
Applicant: ST MICROELECTRONICS SRL
Inventor： OTTINI DANIELE , BRUCCOLERI MELCHIORRE , BOLLATI GIACOMINO , DEMICHELI MARCO
Abstract: PROBLEM TO BE SOLVED: To provide a flash analog/digital converter capable of outputting a temperature measurement digital code. SOLUTION: This flash analog/digital converter is provided with a bank composed of comparators (COMPi) provided with differential output for generating a temperature measurement code and 3-input (A, B and C) logical NOR gates (NORj) and is provided with a passive interface respectively composed of the plural pieces of voltage dividers (Ra-Rb) connected between the non- inverted output (out-p) of the respective comparators (COMPi) and the inverted output (out-n) of the comparators (COMPi+1) of the higher order of the bank. The corresponding logical NOR gate (NORj) of the bank is provided with first input (A) connected to the inverted output (out-n) of the respective comparators (COMPi-1), second input (B) connected to the non-inverted output (out-p) of the comparators (COMPi) of the higher order and third input (C) connected to the intermediate tap of the voltage dividers (Ra-Rb).
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5.发明专利
公开(公告)号：JP2000173186A
公开(公告)日：2000-06-23
申请号：JP34210599
申请日：1999-12-01
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , DEMICHELI MARCO , OTTINI DANIELE , SAVO ALESSANDRO
Abstract: PROBLEM TO BE SOLVED: To prevent the generation of accidental patterns in a frequency domain by individually controlling two identical offest compensating circuits for two ATOD converters. SOLUTION: An interleave type ATOD converter is constituted of two identical analog digital converters, i.e., one for even bit EVEN-S signal path and one for ATOD-EVEN and odd bit ODD-S signal path and an ATOD-ODD. The offsets of digital analog converters included in the ATOD-EVEN and the ATOD-ODD are independently compensated for by the loop constituted of offset compensation stages and OFFSET-EVEN-STAGE and OFFSET-ODD- STAGE controlled by a digital post process blocks through a dedicated digital analog converter DA-OFF-E and a DAC-OFF-O.
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Patent Agency Ranking
公开(公告)号：JP2000166237A
公开(公告)日：2000-06-16
申请号：JP11667499
申请日：1999-04-23
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , OTTINI DANIELE , DEMICHELI MARCO , BOLLATI GIACOMINO
Abstract: PROBLEM TO BE SOLVED: To reduce higher harmonics and dynamic distortion by receiving a differential logical synchronizing signal at the input terminal of a timing circuit, and supplying the first differential timing signal to a track-and-hold stage and the second differential timing signal to a flip flop, respectively. SOLUTION: Differential logical synchronizing signals Clk+, Clk- are received at the input terminal of a timing circuit, and the first differential timing signals TClK+, TClK- are outputted to a differential track-and-hold stage TandH at an output terminal. The second differential timing signals DClK+, DClK- are outputted to a flip flop LATCH-ECL at the output terminal of the timing circuit. The differential track-and-hold stage TandH tracks differential analog input signals IN+, IN- during the tracking phase of the first differential timing signals TClK+, TClK-. The differential flip flop LaATCH-ECL outputs the third differential logical control signals S+, S-.
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公开(公告)号：JPH07182791A
公开(公告)日：1995-07-21
申请号：JP30156994
申请日：1994-11-10
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , GADDUCCI PAOLO , DEMICHELI MARCO , ALINI ROBERTO
Abstract: PURPOSE: To facilitate the decoder of an operation mode by programming one of the output stream of the single bit of decoded data and the dual bit output stream of the decoded data. CONSTITUTION: The second re-timed output signals of a flip-flop B are supplied to the other input 1 of a MUX OUT multiplexer and the input of a forth flip- flop BB and the signals are sampled as the flip-flop AA by a second fractional clock frequency VCO/3. In this case, by performing different selection between the two inputs of an output multiplexers and selecting the one input, a single bit decoding NRZ stream becomes utilizable in the output of this decoder.
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公开(公告)号：DE69330957T2
公开(公告)日：2002-04-04
申请号：DE69330957
申请日：1993-11-10
Applicant: ST MICROELECTRONICS SRL
Inventor： MOLONEY DAVID , GADDUCCI PAOLO , DEMICHELI MARCO , ALINI ROBERTO
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公开(公告)号：DE69519663T2
公开(公告)日：2001-04-26
申请号：DE69519663
申请日：1995-03-07
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , VAI GIANFRANCO , PORTALURI SALVATORE , DEMICHELI MARCO
Abstract: A fully integrated, phase locked loop (PLL) having improved jitter characteristics exploits the same digital/analog converter (DAC) that is normally used for controlling the time constant of the low pass loop filter for controlling the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground that introduces a third pole in the loop's transfer function. In this way the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant, thus the dumping factor remains constant while the omega o of the PLL is varied.
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公开(公告)号：ITVA990020D0
公开(公告)日：1999-07-16
申请号：ITVA990020
申请日：1999-07-16
Applicant: ST MICROELECTRONICS SRL
Inventor： DEMICHELI MARCO , BOLLATI GIACOMINO , DEMICHELI DAVIDE , MARCHESE STEFANO
IPC: G11B20/10
Abstract: A method is provided for defining programmed values of the boost and cut-off frequency parameters of a low pass filter of pre-equalization, of a read channel for a magnetic medium mass memory device, to ensure optimal functioning conditions of the adaptive filter of final equalization. The method includes pre-programming instantaneous digital values of the boost and cut-off frequency parameters of the low pass filter of pre-equalization for each magnetic medium, as a function of purposely sensed instantaneous operating parameters of the adaptive filter that carries out the definitive equalization of the signal during a trim scanning of the magnetic medium.
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