公开(公告)号：JPH0773140A

公开(公告)日：1995-03-17

申请号：JP5280994

申请日：1994-02-25

Applicant: ST MICROELECTRONICS SRL

Inventor： ALINI ROBERTO ,  MOLONEY DAVID ,  GORNATI SILVANO ,  PORTALURI SALVATORE

IPC: G06F13/38 ,  G11C5/00

Abstract: PURPOSE: To reduce the integration area and to accelerate the processing concerning a structure provided with a serial type interface for connection to a data transmission line, by connecting a part of a register to the bundled line and transmitting both a register address and data. CONSTITUTION: A decoded address latch 5 stores the output state of an address decoder 4 until the other address is transmitted through a multiplex bus 2. Only when this address is the address of a designated data register 1, according to the output of this latch 5, data transmitted after this address are written in this register. A write line 9 transmits a data write signal through a logic gate 7 of AND type. A data read circuit means 3 reads data out of this register 1 so as to repeat data from the multiplex bus 2. Only when the transmitted address is as prescribed, a read command starts reading from this register 1.

公开(公告)号：JPH07176138A

公开(公告)日：1995-07-14

申请号：JP25471694

申请日：1994-09-21

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  BETTI GIORGIO ,  ALINI ROBERTO

IPC: G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14

Abstract: PURPOSE: To prevent the generation of errors by the transmission delay of signals by storing bits finally processed in a second combinational logic network (RC1) in a shift register, predicting the time when (n) bits are process in a first RC1 and synthesizing the signals in a second RC2. CONSTITUTION: The first RC1 processes the Q output tap (6:0) value of an FF for forming the shift register SR prior to the processing by the second RC2 of the corresponding bit for the complete two cycles of a synchronous block signal VCO. In order to secure the utilization of the entire cycle of the clock signal VCO which is a corresponding decoding value ND1 in the input D of the output register (FF) of a decoding NRZ output stream, a frequency which is partial compared to the base synchronous clock signal VCO in front of the rising front of a first clock signal and matched with the bit number ratio of input and output streams is provided. The bit finally processed in the RC2 is tentatively stored in the shift registers Q1-Q7, the time when the (n) bits are processed in the RC1 is predicted and the signals are synthesized in the RC2.

公开(公告)号：JPH0879006A

公开(公告)日：1996-03-22

申请号：JP20722395

申请日：1995-08-14

Applicant: ST MICROELECTRONICS SRL

Inventor： BRIANTI FRANCESCO ,  ALINI ROBERTO ,  PISATI VALERIO ,  GADDUCCI PAOLO

IPC: H03H11/04

Abstract: PROBLEM TO BE SOLVED: To constitute a fourth cell which operates with a low supply power, does not require any floating capacitance, and has a low capacitance load at its input terminal. SOLUTION: A high-pass filter constituted of a current generating circuit 29 which is particularly used for high frequencies, has at least each one of input terminal IN and output terminal OUT, between which a transfer function (Fdt) is formed, incorporates serially arranged transconductance stages 2-5, is connected between a pair of stages 2 and 3 of a fourth cell 18 and a reference voltage (GND), and generates variable currents iK1 and iK2 . The circuit 29 makes the introduction of a programmable zero to the transfer function (Fdt) of the filter 20 possible.

公开(公告)号：JPH0865064A

公开(公告)日：1996-03-08

申请号：JP19561095

申请日：1995-07-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PISATI VALERIO ,  ALINI ROBERTO ,  CASTELLO RINALDO ,  VAI GIANFRANCO

IPC: H03F3/343 ,  H03F3/45 ,  H03G1/00 ,  H03H11/24

Abstract: PROBLEM TO BE SOLVED: To control the gain of integrator with built-in transconductor by changing the output resistance of active load. SOLUTION: This device comprises a transconductance stage 3 having two input terminals I1 and I2 at least and two output terminals O1 and O2 at least and provided with an active load 4 connected to the output terminals O1 and O2 on the transconductance stage 3 and control circuit 5 for active load 4 connected between the output terminals O1 and O2 and the active load 4.

公开(公告)号：JPH06196948A

公开(公告)日：1994-07-15

申请号：JP21157793

申请日：1993-08-26

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTELLO RINALDO ,  ALINI ROBERTO ,  REZZI FRANCESCO ,  PISATI VALERIO

IPC: H03F1/32 ,  H03F3/45 ,  H03H11/04

Abstract: PURPOSE: To provide a mutual conductor stage for dealing with a high frequency signal. CONSTITUTION: A mutual conductor stage 1 has signal input parts A and B and signal output parts U1 and U2 and is provided with a pair of FET (M1 and M2 ) sharing gates G1 and G2 and sources S1 and S2 , and its output is composed of a pair of bipolar transistors Q1 and Q2 connected to these FET M1 and M2 .

公开(公告)号：JPH07320404A

公开(公告)日：1995-12-08

申请号：JP11572495

申请日：1995-05-15

Applicant: ST MICROELECTRONICS SRL

Inventor： ZUFFADA MAURIZIO ,  GADDUCCI PAOLO ,  MOLONEY DAVID ,  ALINI ROBERTO

IPC: G11B5/09 ,  G11B20/10

Abstract: PURPOSE: To obtain a partial response signal (PRML) device by maximum likelihood sequence detection displaying no conventional fault. CONSTITUTION: This device has a variable gain input amplifier 21, a low-pass analog filter 22, a transversal continuous-time analog filter 23, and two separate parallel sampling channels 24, 34 inserted between the transversal analog filter 23 and a finite run length-non-return-to-zero type decoder 25. These sampling channels 24, 34 have analog-digital converters 26, 36 operated in accordance with sampling sequences, in which these each sampling channel is continued mutually and alternated mutually, and Viterbi detectors 27, 37.

公开(公告)号：JPH07182791A

公开(公告)日：1995-07-21

申请号：JP30156994

申请日：1994-11-10

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  DEMICHELI MARCO ,  ALINI ROBERTO

IPC: G06F3/06 ,  G11B20/10 ,  G11B20/14 ,  H03M5/14

Abstract: PURPOSE: To facilitate the decoder of an operation mode by programming one of the output stream of the single bit of decoded data and the dual bit output stream of the decoded data. CONSTITUTION: The second re-timed output signals of a flip-flop B are supplied to the other input 1 of a MUX OUT multiplexer and the input of a forth flip- flop BB and the signals are sampled as the flip-flop AA by a second fractional clock frequency VCO/3. In this case, by performing different selection between the two inputs of an output multiplexers and selecting the one input, a single bit decoding NRZ stream becomes utilizable in the output of this decoder.

公开(公告)号：DE69427479T2

公开(公告)日：2002-01-17

申请号：DE69427479

申请日：1994-11-30

Applicant: ST MICROELECTRONICS SRL

Inventor： BRIANTI FRANCESCO ,  PISATI VALERIO ,  ALINI ROBERTO ,  MOLONEY DAVID

IPC: G05F3/26

公开(公告)号：DE69231151D1

公开(公告)日：2000-07-13

申请号：DE69231151

申请日：1992-08-26

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTELLO RINALDO ,  ALINI ROBERTO ,  REZZI FRANCESCO ,  PISATI VALERIO

IPC: H03F1/32 ,  H03F3/45 ,  H03H11/04

公开(公告)号：DE69327053D1

公开(公告)日：1999-12-23

申请号：DE69327053

申请日：1993-09-21

Applicant: ST MICROELECTRONICS SRL

Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  BETTI GIORGIO ,  ALINI ROBERTO

IPC: G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14

Abstract: In a decoder for decoding a serial data stream, employing an extracted base clock signal, synchronous with an input, coded, serial data stream, a fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary clock signal for synthesizing a pre-decoded value produced by a first combinative logic network within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop, a pipelined operation is implemented by momentarily storing the bits that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock the processing by said first combinative network of the n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the raising front of the outpunt sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating spead may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.