公开(公告)号：DE69631583D1

公开(公告)日：2004-03-25

申请号：DE69631583

申请日：1996-04-30

Applicant: ST MICROELECTRONICS SRL

Inventor： MACCARRONE MARCO ,  GHEZZI STEFANO ,  BRANCHETTI MAURIZIO

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/06

Abstract: The present invention concerns a redundant UPROM cell (1) incorporating at least one memory element (P0) of the EPROM or flash type having a control terminal (CG) and a conduction terminal (X) to be biased, a register (2) with inverters connected to the memory element and MOS transistors (M1,M3) connecting said memory element (P0) with a reference low voltage power supply (Vdd). There is provided a precharge network (5) for the conduction terminal (X) of the flash cell and said network (5) incorporates a complementary pair of transistors (M4,M5). The second transistor (M5) of said pair (M4,M5) is a natural N-channel MOS type. With the UPROM cell (1) is associated a circuit portion (10) for generating at output (U) a live signal (UPCH) to be applied to the control terminal of the second transistor (M5) with the portion (10) comprising a timing section (7) and a generation section (8) for said second live signal (UPCH).

公开(公告)号：DE69619112D1

公开(公告)日：2002-03-21

申请号：DE69619112

申请日：1996-10-11

Applicant: ST MICROELECTRONICS SRL

Inventor： GHILARDELLI ANDREA ,  MULATTI JACOPO ,  GHEZZI STEFANO

IPC: H02M3/07