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    NEGATIVE ELECTRIC CHARGE PUMP
    1.
    发明专利
    NEGATIVE ELECTRIC CHARGE PUMP 失效

    公开(公告)号：JPH10303311A

    公开(公告)日：1998-11-13

    申请号：JP30446697

    申请日：1997-11-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHILARDELLI ANDREA ,  MULATTI JACOPO ,  BRANCHETTI MAURIZIO

    IPC: H01L21/8247 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/788 ,  H01L29/792 ,  H02M3/07

    Abstract: PROBLEM TO BE SOLVED: To improve efficiency of an electric charge pump by providing each stage of the second group with a joint diode comprising a first electrode connected to an input terminal and a second electrode connected to an output terminal and a second capacitor comprising a first polar plate connected to an output terminal and a second polar plate driven by a digital signal. SOLUTION: Between an output terminal O and an input terminal of an electric charge pump connected to a ground, four stages S1, S2, S3', and S4' are connected in series. Then, with a first group stage as S1 and S2 while a second group stage S3' and S4', a joint diode D comprising a first electrode connected to an input terminal of the second group S3' and a second electrode connected to an output terminal of the S3' is provided, and a second capacitor CL' comprising a first polar plate connected to the output terminal of the S3' and S4' and a second polar plate driven by respective phase signals B' and D' is provided.

    2.
    发明专利
    未知

    公开(公告)号：DE69733603D1

    公开(公告)日：2005-07-28

    申请号：DE69733603

    申请日：1997-01-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHILARDELLI ANDREA ,  MULATTI JACOPO ,  BRANCHETTI MAURIZIO

    IPC: H02M3/07

    Abstract: A negative charge pump circuit comprises a plurality of charge pump stages (S1'-S4') connected in series to each other. Each stage has a stage input terminal (SI) and a stage output terminal (SO). A first stage (S1') has the stage input terminal (SI) connected to a reference voltage, a final stage (S4') has the stage output terminal (SO) operatively connected to an output terminal (O) of the charge pump at which a negative voltage is developed; intermediate stages (S2' ,S3') have the respective stage input terminal (SI) connected to the stage output terminal (SO) of a preceding stage and the respective stage output terminal connected to the stage input terminal of a following stage. Each stage (S1'-S4') comprises a first N-channel MOSFET (M1') with a first electrode connected to the stage input terminal (SI) and a second electrode connected to the stage output terminal (SO), a second N-channel MOSFET (M2') with a first electrode connected to the stage output terminal (SO) and a second electrode connected to a gate electrode of the first N-channel MOSFET (M1'), a boost capacitor (CP) with one terminal connected to the gate electrode of the first N-channel MOSFET and a second terminal driven by a respective first digital signal (A',C') switching between the reference voltage and a positive voltage supply (VDD), and a second capacitor (CL) with one terminal connected to the charge pump stage output terminal (SO) and a second terminal connected to a respective second digital signal (B',D') switching between the reference voltage and the voltage supply (VDD). A gate electrode of the second N-channel MOSFET (M2') is connected, in the first stage (S1'), to a third digital signal (D') switching between the reference voltage and the voltage supply, while in the remaining stage the gate electrode of the second N-channel MOSFET is connected to the stage input terminal (SI).

    3.
    发明专利
    未知

    公开(公告)号：DE69622149D1

    公开(公告)日：2002-08-08

    申请号：DE69622149

    申请日：1996-03-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRANCHETTI MAURIZIO ,  CONCI ARMANDO ,  GOLLA CARLA

    IPC: G06F11/10

    Abstract: The invention relates to a method of recovering faulty non-volatile memories. This method can be applied to an electrically programmable semiconductor non-volatile memory device being set up as a multi-sectors memory matrix and including selection circuitry for selecting words or individual bytes of the memory. According to this method, the memory matrix is addressed by byte, rather than by memory word, by acting said selection circuitry, whenever the device fails an operation test. The use of a Hamming code of error correction to remedy malfunctions due to manufacture allows the method to be applied to those devices which fail their test and would otherwise be treated as rejects.

    7.
    发明专利
    未知

    公开(公告)号：DE69634509D1

    公开(公告)日：2005-04-28

    申请号：DE69634509

    申请日：1996-04-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  GHEZZI STEFANO ,  BRANCHETTI MAURIZIO

    IPC: H03K17/22

    Abstract: The present invention relates to an electronic power on reset circuit (1) of the type comprising a comparator (2) having at least two inputs and one output (A) for receiving a first reference signal from a generator block (11) and a second signal proportional to a supply voltage (Vdd) from a divider block (12) and for producing at output an initialization signal (INTPOR). Advantageously the output (A) is connected to a third turn off enablement input (10) of the comparator (2) through the series of an inverter pair (I1,I2). The generator block (11) and the divider block (12) also comprise respective turn off enablement inputs (15,13) connected downstream of the inverter pair (I1,I2).

    8.
    发明专利
    未知

    公开(公告)号：DE69622149T2

    公开(公告)日：2002-11-28

    申请号：DE69622149

    申请日：1996-03-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRANCHETTI MAURIZIO ,  CONCI ARMANDO ,  GOLLA CARLA

    IPC: G06F11/10

    Abstract: The invention relates to a method of recovering faulty non-volatile memories. This method can be applied to an electrically programmable semiconductor non-volatile memory device being set up as a multi-sectors memory matrix and including selection circuitry for selecting words or individual bytes of the memory. According to this method, the memory matrix is addressed by byte, rather than by memory word, by acting said selection circuitry, whenever the device fails an operation test. The use of a Hamming code of error correction to remedy malfunctions due to manufacture allows the method to be applied to those devices which fail their test and would otherwise be treated as rejects.

    10.
    发明专利
    未知

    公开(公告)号：DE69631583D1

    公开(公告)日：2004-03-25

    申请号：DE69631583

    申请日：1996-04-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MACCARRONE MARCO ,  GHEZZI STEFANO ,  BRANCHETTI MAURIZIO

    IPC: G11C16/04 ,  G11C16/24 ,  G11C16/06

    Abstract: The present invention concerns a redundant UPROM cell (1) incorporating at least one memory element (P0) of the EPROM or flash type having a control terminal (CG) and a conduction terminal (X) to be biased, a register (2) with inverters connected to the memory element and MOS transistors (M1,M3) connecting said memory element (P0) with a reference low voltage power supply (Vdd). There is provided a precharge network (5) for the conduction terminal (X) of the flash cell and said network (5) incorporates a complementary pair of transistors (M4,M5). The second transistor (M5) of said pair (M4,M5) is a natural N-channel MOS type. With the UPROM cell (1) is associated a circuit portion (10) for generating at output (U) a live signal (UPCH) to be applied to the control terminal of the second transistor (M5) with the portion (10) comprising a timing section (7) and a generation section (8) for said second live signal (UPCH).

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