公开(公告)号：ITVA20050006A1

公开(公告)日：2006-08-09

申请号：ITVA20050006

申请日：2005-02-08

Applicant: ST MICROELECTRONICS SRL

Inventor： CASTORINA ALESSANDRO ,  GIRLANDO GIOVANNI ,  MOTTA CARLA ,  PALMISANO GIUSEPPE

公开(公告)号：IT201800003127A1

公开(公告)日：2019-08-28

申请号：IT201800003127

申请日：2018-02-28

Applicant: ST MICROELECTRONICS SRL

Inventor： FINOCCHIARO ALESSANDRO ,  GIRLANDO GIOVANNI

IPC: G06K20060101

公开(公告)号：ITUB20156293A1

公开(公告)日：2017-06-04

申请号：ITUB20156293

申请日：2015-12-04

Applicant: ST MICROELECTRONICS SRL

Inventor： PAGANI ALBERTO ,  GIRLANDO GIOVANNI ,  ZIGLIOLI FEDERICO GIOVANNI ,  FINOCCHIARO ALESSANDRO

公开(公告)号：ITMI20120542A1

公开(公告)日：2013-10-04

申请号：ITMI20120542

申请日：2012-04-03

Applicant: ST MICROELECTRONICS SRL

Inventor： FINOCCHIARO ALESSANDRO ,  GIRLANDO GIOVANNI ,  MURARI BRUNO

公开(公告)号：DE602004026841D1

公开(公告)日：2010-06-10

申请号：DE602004026841

申请日：2004-05-31

Applicant: ST MICROELECTRONICS SRL

Inventor： COPANI TINO ,  SMERZI SANTO ALESSANDRO ,  GIRLANDO GIOVANNI ,  PALMISANO GIUSEPPE

IPC: H03K23/66

Abstract: A prescaling stage is described of the type comprising at least one bistable circuit in turn including respective master and slave portions (2, 3) inserted between a first and a second voltage reference (Vcc, GND) and feedback connected to each other. Each portion is provided with at least one differential stage (4, 5) supplied by the first voltage reference (Vcc) and connected, by means of a transistor stage (52, 53), to the second voltage reference (GND), as well as a differential pair (6, 7) of cross-coupled transistors, supplied by output terminals of the differential stage (4, 5) and connected, by means of the transistor stage (52, 53), to the second voltage reference (GND). Advantageously according to the invention, each master and slave portion (2, 3) comprises at least one degeneracy capacity (C2, C3) inserted in correspondence with respective terminals of the transistors of the differential pair (6, 7).

公开(公告)号：DE602005018319D1

公开(公告)日：2010-01-28

申请号：DE602005018319

申请日：2005-01-25

Applicant: ST MICROELECTRONICS SRL

Inventor： COPANI TINO ,  SMERZI SANTO ALESSANDRO ,  GIRLANDO GIOVANNI ,  PALMISANO GIUSEPPE

IPC: H03F3/45

公开(公告)号：DE69834499T2

公开(公告)日：2007-04-19

申请号：DE69834499

申请日：1998-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMISANO GIUSEPPE ,  FERLA GIUSEPPE ,  GIRLANDO GIOVANNI

IPC: H03F1/56 ,  H03F1/22

Abstract: The amplifier stage (50) comprises a first (2) and a second (3) transistor, connected in series to each other between a first (4) and a second (5) reference potential line. The first transistor (2) has a control terminal (10), connected to an input (11) of the amplifier stage (50) through a first inductor (12), a first terminal (15), connected to the second reference potential line (5) through a second inductor (16), and a third terminal (17) connected to a first terminal of the second transistor (3). The second transistor has a second terminal (21) forming an output of the amplifier stage (50), and connected to the first reference potential line (4) through a load resistor (22). To improve the noise figure, a matching capacitor (51) is connected between the control terminal (10) and the first terminal (15) of the first transistor (2).

公开(公告)号：DE69834499D1

公开(公告)日：2006-06-14

申请号：DE69834499

申请日：1998-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMISANO GIUSEPPE ,  FERLA GIUSEPPE ,  GIRLANDO GIOVANNI

IPC: H03F1/56 ,  H03F1/22

Abstract: The amplifier stage (50) comprises a first (2) and a second (3) transistor, connected in series to each other between a first (4) and a second (5) reference potential line. The first transistor (2) has a control terminal (10), connected to an input (11) of the amplifier stage (50) through a first inductor (12), a first terminal (15), connected to the second reference potential line (5) through a second inductor (16), and a third terminal (17) connected to a first terminal of the second transistor (3). The second transistor has a second terminal (21) forming an output of the amplifier stage (50), and connected to the first reference potential line (4) through a load resistor (22). To improve the noise figure, a matching capacitor (51) is connected between the control terminal (10) and the first terminal (15) of the first transistor (2).