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    SUBSTRATE-LEVEL ASSEMBLY FOR AN INTEGRATED DEVICE, MANUFACTURING PROCESS THEREOF AND RELATED INTEGRATED DEVICE
    1.
    发明申请
    SUBSTRATE-LEVEL ASSEMBLY FOR AN INTEGRATED DEVICE, MANUFACTURING PROCESS THEREOF AND RELATED INTEGRATED DEVICE 审中-公开
    用于集成设备的基板级组件，其制造工艺以及相关的集成设备

    公开(公告)号：WO2007042336A2

    公开(公告)日：2007-04-19

    申请号：PCT/EP2006064298

    申请日：2006-07-14

    Applicant: ST MICROELECTRONICS SRL ,  COMBI CHANTAL ,  VIGNA BENEDETTO ,  ZIGLIOLI FEDERICO GIOVANNI ,  BALDO LORENZO ,  MAGUGLIANI MANUELA ,  LASALANDRA ERNESTO ,  RIVA CATERINA

    Inventor： COMBI CHANTAL ,  VIGNA BENEDETTO ,  ZIGLIOLI FEDERICO GIOVANNI ,  BALDO LORENZO ,  MAGUGLIANI MANUELA ,  LASALANDRA ERNESTO ,  RIVA CATERINA

    IPC: B81B7/02

    CPC classification number: B81B7/0061 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C1/0023 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H04R1/04 ,  H04R19/005 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: In a substrate-level assembly (22), a device substrate (20) of semiconductor material has a top face (20a) and houses a first integrated device (1; 16), in particular provided with a buried cavity (3), formed within the device substrate (20), and with a membrane (4), suspended over the buried cavity (3) in the proximity of the top face (20a). A capping substrate (21) is coupled to the device substrate (20) above the top face (20a) so as to cover the first integrated device (1; 16), in such a manner that a first empty space (25) is provided above the membrane (4). Electrical-contact elements (28a, 28b) electrically connect the integrated device (1; 16) with the outside of the substrate-level assembly (22). In one embodiment, the device substrate (20) integrates at least a further integrated device (1', 10) provided with a respective membrane (4'); and a further empty space (25'), fluidically isolated from the first empty space (25), is provided over the respective membrane (4') of the further integrated device (1', 10).

    Abstract translation: 在衬底级组件（22）中，半导体材料的器件衬底（20）具有顶面（20a）并容纳第一集成器件（1; 16），所述第一集成器件特别设置有埋入腔（3） 在器件衬底（20）内并且具有在顶面（20a）附近悬置在掩埋腔（3）上的膜（4）。 封盖衬底（21）在顶面（20a）上方与器件衬底（20）耦合，以便以这样的方式覆盖第一集成器件（1; 16）：提供第一空的空间（25） 在膜（4）上方。 电接触元件（28a，28b）将集成装置（1; 16）与衬底级组件（22）的外部电连接。 在一个实施例中，所述装置基底（20）集成了至少另一个集成装置（1'，10），所述集成装置设置有相应的膜（4'）; 并且在另一集成装置（1'，10）的相应的膜（4'）上设置与第一空的空间（25）流体隔离的另一个空的空间（25'）。

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