公开(公告)号：DE69528961D1

公开(公告)日：2003-01-09

申请号：DE69528961

申请日：1995-03-09

Applicant: ST MICROELECTRONICS SRL

Inventor： CONTIERO CLAUDIO ,  GALBIATI PAOLA ,  PALMIERI MICHELE

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8247 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L27/115 ,  H01L29/08 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

公开(公告)号：DE69505348T2

公开(公告)日：1999-03-11

申请号：DE69505348

申请日：1995-02-21

Applicant: ST MICROELECTRONICS SRL

Inventor： DE PETRO RICCARDO ,  PALMIERI MICHELE ,  GALBIATI PAOLA ,  CONTIERO CLAUDIO

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: A high voltage lateral MOSFET transistor structure constituted by various interdigitated modular elements formed on a layer of monocrystaline silicon is described together with a process for its fabrication. To save area of silicon and to reduce the specific resistivity RDS on enriched drain regions (16) are formed by implanting doping material (N) in the silicon through apertures in the field oxide (11) obtained with a selective anisotropic etching by utilising as a mask the strips of polycrystaline silicon (14) which serve as gate electrodes and field electrodes.

公开(公告)号：IT1306973B1

公开(公告)日：2001-10-11

申请号：ITTO990009

申请日：1999-01-12

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  PALMIERI MICHELE

IPC: H01L21/762 ,  H01L21/8234

Abstract: A process for forming insulating structures for integrated circuits that includes depositing a silicon oxide layer; shaping the silicon oxide layer to form first delimiting walls of the insulating regions substantially perpendicular to the substrate; and shaping the silicon oxide layer to form second delimiting walls inclined with respect to the substrate. The first walls have an angle of between approximately 70° and 110° with respect to the surface of the substrate; the second walls have an angle of between approximately 30° and 70° with respect to the surface of the substrate 11. The first delimiting walls are formed using a first mask and etching anisotropically first portions of the oxide layer; the second delimiting walls are formed using a second mask and carrying out a damage implantation for damaging second portions of the oxide layer and subsequently wet etching the damaged portions.

公开(公告)号：ITTO990009A1

公开(公告)日：2000-07-12

申请号：ITTO990009

申请日：1999-01-12

Applicant: ST MICROELECTRONICS SRL

Inventor： DEPETRO RICCARDO ,  PALMIERI MICHELE

IPC: H01L21/762 ,  H01L21/8234

Abstract: A process for forming insulating structures for integrated circuits that includes depositing a silicon oxide layer; shaping the silicon oxide layer to form first delimiting walls of the insulating regions substantially perpendicular to the substrate; and shaping the silicon oxide layer to form second delimiting walls inclined with respect to the substrate. The first walls have an angle of between approximately 70° and 110° with respect to the surface of the substrate; the second walls have an angle of between approximately 30° and 70° with respect to the surface of the substrate 11. The first delimiting walls are formed using a first mask and etching anisotropically first portions of the oxide layer; the second delimiting walls are formed using a second mask and carrying out a damage implantation for damaging second portions of the oxide layer and subsequently wet etching the damaged portions.

公开(公告)号：DE69415500T2

公开(公告)日：1999-05-20

申请号：DE69415500

申请日：1994-03-31

Applicant: ST MICROELECTRONICS SRL

Inventor： PALMIERI MICHELE ,  DEPETRO RICCARDO

IPC: H01L21/8249 ,  H01L21/225 ,  H01L21/265 ,  H01L21/329 ,  H01L21/331 ,  H01L21/337 ,  H01L21/822 ,  H01L27/06 ,  H01L29/73 ,  H01L29/866 ,  H01L21/82

Abstract: A method is disclosed for forming a first region (32) with conductivity of a first type (N) and second, buried region (30) with conductivity of a second type (P) which forms a junction with the first region (32). By first and second doping steps, impurities of a first (As) and a second (B) type are successively introduced into a silicon chip. A high-temperature treatment causes the impurities thus introduced to diffuse and form said first (32) and second (30) regions. In order to provide a buried region whose concentration and/or depth are little dependent on process parameters, the second doping step comprises a first sub-step of low dosage and high energy implantation, and a second sub-step of low dosage and high energy implantation. The dosages and energies are such that they will not compensate or reverse the type of conductivity of the first region (32), and such that the concentration in the second region (30) will be substantially due to the second implantation step only. This process is compatible with a CMOS-process. The buried junction can be used for a Zener diode, a vertical bipolar transistor or a JFET.