公开(公告)号：ITVA20020047A1

公开(公告)日：2004-03-28

申请号：ITVA20020047

申请日：2002-09-27

Applicant: ST MICROELECTRONICS SRL

Inventor： PASOTTI MARCO ,  POLES MARCO ,  QUARANTELLI MICHELE ,  ROLANDI PIER LUIGI

IPC: H02M20060101

公开(公告)号：IT1319614B1

公开(公告)日：2003-10-20

申请号：ITMI20002807

申请日：2000-12-22

Applicant: ST MICROELECTRONICS SRL

Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  DE SANDRE GUIDO ,  IEZZI DAVID ,  POLES MARCO ,  ROLANDI PIERLUIGI

IPC: G11C8/08 ,  G11C16/12

公开(公告)号：ITRM20010525D0

公开(公告)日：2001-08-30

申请号：ITRM20010525

申请日：2001-08-30

Applicant: ST MICROELECTRONICS SRL

Inventor： GUAITINI GIOVANNI ,  PASOTTI MARCO ,  DE SANDRE GUIDO ,  IEZZI DAVID ,  POLES MARCO ,  ROLANDI PIERLUIGI

IPC: G11C16/08 ,  G11C16/16

Abstract: A non-volatile semiconductor memory device including an output connected to a row line and two supply terminals. Each elementary stage has an upper branch with a p-channel MOS transistor and a lower branch with an n-channel MOS transistor. In order to permit the memory to be erased line by line without having to use components capable of withstanding high voltages, each elementary stage has two supplementary MOS transistors, namely an n-channel transistor in the upper branch and a p-channel transistor in the lower branch. In this way it becomes possible to bias the elementary stages in such a manner the in the reading and programming phases the upper branch will function as pull-up and the lower branch as pull-down, while in the erasure phase the upper branch functions as pull-down and the lower branch as pull-up.