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    1.
    发明专利
    未知

    公开(公告)号：DE69828966D1

    公开(公告)日：2005-03-17

    申请号：DE69828966

    申请日：1998-09-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  LHERMET FRANK ,  ROLANDI PIER LUIGI

    IPC: G11C11/56 ,  G11C16/34 ,  G11C16/06

    Abstract: The method includes restoring the charge lost from memory cells, such as to restore the original voltage levels, within a time equivalent to the retention time. The decision concerning when the memory is to be restored is taken for example when the memory is switched on, based on the time elapsed since the previous programming/restoration, or based on the difference between the present threshold voltage of the reference cells and the original threshold voltage of the (suitably stored) reference cells, or when predetermined operating conditions occur. This makes it possible to prolong the life of nonvolatile memories, in particular of multilevel type, wherein the retention time decreases as the number of levels (bits/cell) is increased.

    4.
    发明专利
    未知

    公开(公告)号：DE60102203D1

    公开(公告)日：2004-04-08

    申请号：DE60102203

    申请日：2001-12-13

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANI ,  IEZZI DAVID ,  POLES MARCO

    IPC: G11C11/56

    Abstract: It is described a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels. The method comprises the phases of: initially programming a cell threshold value to a first set of levels [0;(m-1)] being m a submultiple of the plurality of levels of the multilevel cell; reprogramming without erasing another set of levels [m;(2m-1)] containing the same number m of levels as the first set; reiterating the reprogramming without erasing phase until the levels of the multilevel cell are exhausted. It is also described a multilevel memory device of the type comprising a plurality of multilevel memory cells organized into sectors, the sectors being themselves split into a plurality of data units wherein a data updating operation is performed in parallel, the data units being programmed by means of the programming method.

    5.
    发明专利
    未知

    公开(公告)号：ITTO990944A1

    公开(公告)日：2001-04-30

    申请号：ITTO990944

    申请日：1999-10-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DE SANDRE GUIDO ,  PASOTTI MARCO ,  ROLANDI PIER LUIGI ,  GUAITINI GIOVANNI

    IPC: G11C11/56 ,  G11C16/28

    Abstract: A reading circuit having an array branch connected via an array bit line to an array memory cell, the content of which is to be read; a reference branch connected via a reference bit line to a current generator stage supplying a reference current; a current/voltage converter stage connected to the array branch and to the reference branch, and supplying at an array node and at a reference node respectively an array potential and a reference potential, which are correlated to the currents flowing respectively in the array branch and in the reference branch; a comparator stage connected to the array node and the reference node for comparing the array and reference potentials; a sample and hold stage arranged between the array node and the comparator stage and selectively operable to sample and hold the array potential; and a switching off stage for switching off the array branch.

    6.
    发明专利
    未知

    公开(公告)号：ITMI990859A1

    公开(公告)日：2000-10-23

    申请号：ITMI990859

    申请日：1999-04-23

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

    IPC: G11C16/16

    Abstract: A method for erasing non volatile memories, in particular flash cells, that includes applying erasing pulses to the cells to be erased and to verify, after each pulse, the value of the threshold voltage of the cells. The erasing pulses are provided to the cells as long as the respective values of the threshold voltage are greater than the new values of threshold voltage corresponding to new data to be rewritten in the cells to be erased.

    10.
    发明专利
    未知

    公开(公告)号：IT1312471B1

    公开(公告)日：2002-04-17

    申请号：ITMI991017

    申请日：1999-05-11

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PASOTTI MARCO ,  GUAITINI GIOVANNI ,  ROLANDI PIER LUIGI

    IPC: G11C11/56 ,  G11C16/34

    Abstract: A method for the in-writing verification of the threshold value of the multilevel cells suitable to memorize n bits each, that provides for the utilization of a sense amplifier containing a respective successive approximation register. An output signal of a comparison circuit provides for the loading of the datum to be programmed in the cell being selected, after which a programming pulse is applied and the comparison between the reference current corresponding to said datum and the current that flows in the cell is carried out. The application of the programming pulse and the performance of the comparison are then repeated until it is verified that the current of the cell is smaller than the reference current.

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