公开(公告)号：ITTO20010529A1

公开(公告)日：2002-12-02

申请号：ITTO20010529

申请日：2001-06-01

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  ZANARDI STEFANO ,  PICCA MASSIMILIANO ,  RAVASIO ROBERTO

IPC: G06F11/10 ,  G06F12/00

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

公开(公告)号：DE602004026707D1

公开(公告)日：2010-06-02

申请号：DE602004026707

申请日：2004-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： MARELLI ALESSIA ,  RAVASIO ROBERTO ,  MICHELONI RINO

IPC: H03M13/15 ,  G06F11/10

Abstract: The invention relates to a method and system for correcting errors in multilevel memories using binary BCH codes. The number of errors is estimated by analyzing the syndrome components (5). If the number of estimated errors is one, then simple decoding for a Hamming code is performed. Otherwise, conventional decoding of the BCH code is carried out (2,3). This avoids the computation of the error locator polynomial and its roots in the presence of only one error and, thus, reduces the average decoding complexity.

公开(公告)号：DE602005012625D1

公开(公告)日：2009-03-19

申请号：DE602005012625

申请日：2005-07-22

Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS SRL

Inventor： BOVINO ANGELO ,  ALTIERI VINCENZO ,  RAVASIO ROBERTO ,  MICHELONI RINO ,  DE MATTEIS MARIO

IPC: G11C11/56

Abstract: Multi-level programming (30-42) allows for writing a first and a second bit in selected cells (3) by separately programming (30-32) a first bit (LSB) from a second bit (MSB). Programming (30-32) of the first bit determines a shifting (32) from a first threshold level (A) to a second threshold level (B); programming (36-42) of the second bit requires a preliminary reading (36-40) to detect whether the first bit (LSB) has been modified; performing a first writing step (42) to bring the cell to a third threshold voltage (C) if the first bit has been modified and performing a second writing step (42) to bring the selected cell to a fourth threshold voltage (D) different from the third threshold level if the first bit has not been modified. The memory array (2) divided into a first portion (2a) where data are stored using multiple threshold levels corresponding to a plurality of bits, and a second portion (2b) where data are stored using two threshold levels corresponding to a single bit. For increasing reading and program reliability, during preliminary reading (40) of the second portion (2b) a reading result is forced to correspond to the first threshold level.

公开(公告)号：ITTO20010529D0

公开(公告)日：2001-06-01

申请号：ITTO20010529

申请日：2001-06-01

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  ZANARDI STEFANO ,  PICCA MASSIMILIANO ,  RAVASIO ROBERTO

IPC: G06F11/10 ,  G06F12/00

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.