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    1.
    发明专利
    未知

    公开(公告)号：DE602006008480D1

    公开(公告)日：2009-09-24

    申请号：DE602006008480

    申请日：2006-09-13

    Applicant: HYNIX SEMICONDUCTOR INC ,  ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  RAVASIO ROBERTO ,  MARELLI ALESSIA

    IPC: G06F11/10 ,  G06F11/20

    Abstract: Basic redundancy information is non volatily stored in a reserved area (that is an area of the array that is not addressable by the user of the device) of the addressable area of the array and is copied on volatile storage supports at every power-on of the memory device. The unpredictable though statistically inevitable presence of fail array elements also in such a reserved area of the memory array that would corrupt the basic redundancy information as established during the test-on wafer (EWS) phase of the fabrication process and thus increasing the number of rejects, lowering the yield of the fabrication process, is effectively overcome by writing the basic redundancy data in the reserved area of the array with an ECC technique, using a certain error correction code that may be chosen among so-called majority codes 3, 5, 7, 15 and the like or Hamming code for 1, 2, 3 or more errors, in function of the fail probability of a memory cell as determined by the testing on wafer of the devices during fabrication (fail probability of the specific fabrication process used). A significant area saving is achieved compared to the use of fuse arrays and other known approaches.

    7.
    发明专利
    未知

    公开(公告)号：DE602006009662D1

    公开(公告)日：2009-11-19

    申请号：DE602006009662

    申请日：2006-08-24

    Applicant: ST MICROELECTRONICS SRL ,  HYNIX SEMICONDUCTOR INC

    Inventor： MICHELONI RINO ,  CRIPPA LUCA ,  RAVASIO ROBERTO ,  PIO FEDERICO

    IPC: G11C16/34

    Abstract: A method for operating a flash memory device ( 100 ) is proposed. The memory device includes a matrix of memory cells ( 110 ) each one having a programmable threshold voltage (V T ) defining a value stored in the memory cell. The method includes the steps of crasing a block ( 115 ) of memory cells, and compacting the threshold voltages of the memory cells of the block within a predefined compacting range, wherein the step of compacting includes: selecting at least one first memory cell (110 0e ) of the block for writing a target value; restoring the threshold voltage of a subset (110 0e ; 110 1o ) of the memory cells of the block to the compacting range, the subset consisting of the at least one first memory cell (110 0e ) and/or at least one second memory cell of the block (110 1o ) being adjacent to the at least one first memory cell; and at least partially writing the target value into the at least one first memory cell.

    8.
    发明专利
    未知

    公开(公告)号：DE602006006788D1

    公开(公告)日：2009-06-25

    申请号：DE602006006788

    申请日：2006-03-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARELLI ALESSIA ,  INTINI VALERIA ,  RAVASIO ROBERTO ,  MICHELONI RINO

    IPC: G06F11/10 ,  G06F11/14

    Abstract: A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A 0 , A 1 , ..., A LS-1 ) to generate a first recovered string (S 1 ), and performing a first decoding attempt using the first recovered string (S 1 ). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S 2 -S N ) is generated. On the basis of a comparison between the first recovered string (S 1 ) and the second recovered string (S 2 -S N ), a modified string (S M ) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (S M ).

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