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    OUTPUT CIRCUIT FOR INTEGRATED CIRCUIT
    1.
    发明专利
    OUTPUT CIRCUIT FOR INTEGRATED CIRCUIT 失效

    公开(公告)号：JPH11195715A

    公开(公告)日：1999-07-21

    申请号：JP29938198

    申请日：1998-10-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MULATTI JACOPO ,  ZANARDI STEFANO ,  GOLLA CARLA MARIA ,  CONCI ARMANDO

    IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0175

    Abstract: PROBLEM TO BE SOLVED: To reduce the effects of noise exerted to an input stage and internal circuit of an integrated circuit by an output stage of the integrated circuit. SOLUTION: An output stage for an integrated circuit is provided with a first transistor means P2 and a second transistor means N2, serially connected between a first external voltage Vcc and a second external voltage Gnd on the outside of the integrated circuit 100 respectively, through a first and a second electric connection means L2 and L4. The first transistor means P2 transmits the first external voltage Vcc to an output line 5 of the integrated circuit, and the second transistor means N2 transmits the second external voltage Gnd to the output line 5 of the integrated circuit. The second transistor means N2 is formed inside a first well 130 of a first conductivity type provided inside a second well 140 of a second conductivity type formed inside a substrate 7 of the first conductivity type. The second well 140 of the second conductive type is connected through a third electric connection means L21 which is different from the first electric connection means L2 to the first external voltage Vcc.

    2.
    发明专利
    未知

    公开(公告)号：DE602004010795T2

    公开(公告)日：2008-12-11

    申请号：DE602004010795

    申请日：2004-06-24

    Applicant: ST MICROELECTRONICS SRL ,  HYNIX SEMICONDUCTOR INC

    Inventor： ZANARDI STEFANO ,  MARTINOZZI GIULIO

    IPC: G11C16/10 ,  G11C16/26

    Abstract: A page buffer (130) for an electrically programmable memory (100) including a plurality of memory cells (110) forming a plurality of memory pages, the page buffer comprising a plurality of storage units (205) for at least temporarily storing data read from or to be written into the memory cells of selected memory pages of said plurality, each storage unit comprising a first latch (230-1) and a second latch (230-2), operatively associated with a selected bit line (BLe,BLo) of memory cells, for reading/programming the data bit from/into a selected memory cell belonging to said bit line, and with a respective data line (I/O-LINE), for transporting the data bit read from a selected memory cell to an output interface (140,I/O) of the memory, in which each of said first and second latches in the storage unit includes: a first input/output terminal (237-1a,237-2a) and a second input/output terminal (237-1b,237-2b); input switching means (280-1a,280-1b,280-2a,280-2b) for loading into the latch the data bit to be written and to be temporarily stored in response to an input control signal (DI-1,DI-2) corresponding to the data bit, the input switching means having an input terminal connected to the respective data line for receiving a set voltage provided therethrough, a first output terminal coupled to the first input/output terminal of the latch and a second output terminal coupled to the second input/output terminal, and a control terminal receiving the input control signal, the input switching means providing the set voltage to the first or second input/output terminal of the latch depending on the data bit to be written; and an output switch device (280-1b,280-2b) for transferring onto the respective data line the read data bit temporarily stored into the latch in response to an output control signal (DO-1,DO-2), the output switch device having a first terminal coupled to one among the first and second input/output terminals of the latch, a second terminal connected to the respective data line and a control terminal receiving the output control signal.

    5.
    发明专利
    未知

    公开(公告)号：DE602004002947D1

    公开(公告)日：2006-12-07

    申请号：DE602004002947

    申请日：2004-07-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PICCA MASSIMILIANO ,  ZANARDI STEFANO

    IPC: G11C29/00

    Abstract: An electrically programmable memory ( 100 ) including: an array ( 105 ) of a plurality of memory cells ( 210 ) arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks (225_1 - 225 K) and each memory block including a plurality of memory pages; means for receiving (106,I/O,112,115) an address corresponding to a respective memory block; selecting means ( 120,125r,195,125r,130,155 ) for selecting the addressed memory block; and means for detecting (REG_1 - REG_K,135,145,147) a failure of the addressed memory block, wherein the means for detecting a failure includes: a plurality of registers (REG_1 - REG_K), each regis (AR, RED ADD) of the failure of the respective memory block; and means for reading ( 135,145,147 ) the register corresponding to the addressed memory block in response to the receiving of the address, and wherein the programmable memory further includes at least one redundant memory block ( RED_1 - RED_M ) of memory cells including a plurality of redundant memory pages, the selecting means selecting the at least one redundant memory block in place of the addressed memory block in response to the reading of the indication of the failure.

    6.
    发明专利
    未知

    公开(公告)号：DE69624230T2

    公开(公告)日：2003-02-13

    申请号：DE69624230

    申请日：1996-07-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  ZANARDI STEFANO ,  GOLLA CARLA

    IPC: H03K19/003 ,  H03K17/00

    Abstract: An output stage (1) for electronic circuits (2) with high voltage tolerance and of the type comprising an output buffer made up of a complementary transistor pair (Pu,Nu) comprising a P-channel MOS pull-up transistor (Pu) and an N-channel MOS pull-down transistor. The transistors are connected together to make up an output terminal (U) of the stage which comprises in addition a switch (6) having an input (8) connected to the output terminal (U) of the stage and an output (9) connected to the control terminal of the pull-up transistor to drive said control terminal in a state of extinction of the output buffer.

    8.
    发明专利
    未知

    公开(公告)号：DE602004002947T2

    公开(公告)日：2007-06-28

    申请号：DE602004002947

    申请日：2004-07-14

    Applicant: ST MICROELECTRONICS SRL

    Inventor： PICCA MASSIMILIANO ,  ZANARDI STEFANO

    IPC: G11C29/00

    Abstract: An electrically programmable memory ( 100 ) including: an array ( 105 ) of a plurality of memory cells ( 210 ) arranged accordingly to a NAND architecture, said memory cells grouped into a plurality of memory blocks (225_1 - 225 K) and each memory block including a plurality of memory pages; means for receiving (106,I/O,112,115) an address corresponding to a respective memory block; selecting means ( 120,125r,195,125r,130,155 ) for selecting the addressed memory block; and means for detecting (REG_1 - REG_K,135,145,147) a failure of the addressed memory block, wherein the means for detecting a failure includes: a plurality of registers (REG_1 - REG_K), each regis (AR, RED ADD) of the failure of the respective memory block; and means for reading ( 135,145,147 ) the register corresponding to the addressed memory block in response to the receiving of the address, and wherein the programmable memory further includes at least one redundant memory block ( RED_1 - RED_M ) of memory cells including a plurality of redundant memory pages, the selecting means selecting the at least one redundant memory block in place of the addressed memory block in response to the reading of the indication of the failure.

    9.
    发明专利
    未知

    公开(公告)号：DE69615149T2

    公开(公告)日：2002-07-04

    申请号：DE69615149

    申请日：1996-03-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GOLLA CARLA MARIA ,  ZAMMATTIO MATTEO ,  ZANARDI STEFANO

    IPC: G11C8/18 ,  H03K5/1534 ,  H03K3/011 ,  H03K3/355 ,  G11C8/00

    Abstract: An address transition detection circuit (30) having a number of cells (1) supplied with respective address signals and output connected in a wired NOR configuration to generate a pulse signal (WN) on detecting transitions of their respective address signals. The pulse signal is supplied to a source stage for generating an address transition signal (ATDO) having a first and second switching edge on receiving the pulse signal. The source stage has a monostable stage (80) for generating an end-of-transition signal (ATDY) with a predetermined delay following reception of the pulse signal; and an output stage (35, 70) connected to the cells (1) and to the monostable stage (80), which generates the first switching edge of the address transition signal (ATDO) on receiving the pulse signal (WN), and the second switching edge on receiving the end-of-transition signal. The monostable stage (80) presents a compensating structure (40, 42, 44) for maintaining the delay in the switching of the end-of-transition signal (ATDY) stable alongside variations in temperature and supply voltage.

    10.
    发明专利
    未知

    公开(公告)号：DE602004010795D1

    公开(公告)日：2008-01-31

    申请号：DE602004010795

    申请日：2004-06-24

    Applicant: ST MICROELECTRONICS SRL ,  HYNIX SEMICONDUCTOR INC

    Inventor： ZANARDI STEFANO ,  MARTINOZZI GIULIO

    IPC: G11C16/10 ,  G11C16/26

    Abstract: A page buffer (130) for an electrically programmable memory (100) including a plurality of memory cells (110) forming a plurality of memory pages, the page buffer comprising a plurality of storage units (205) for at least temporarily storing data read from or to be written into the memory cells of selected memory pages of said plurality, each storage unit comprising a first latch (230-1) and a second latch (230-2), operatively associated with a selected bit line (BLe,BLo) of memory cells, for reading/programming the data bit from/into a selected memory cell belonging to said bit line, and with a respective data line (I/O-LINE), for transporting the data bit read from a selected memory cell to an output interface (140,I/O) of the memory, in which each of said first and second latches in the storage unit includes: a first input/output terminal (237-1a,237-2a) and a second input/output terminal (237-1b,237-2b); input switching means (280-1a,280-1b,280-2a,280-2b) for loading into the latch the data bit to be written and to be temporarily stored in response to an input control signal (DI-1,DI-2) corresponding to the data bit, the input switching means having an input terminal connected to the respective data line for receiving a set voltage provided therethrough, a first output terminal coupled to the first input/output terminal of the latch and a second output terminal coupled to the second input/output terminal, and a control terminal receiving the input control signal, the input switching means providing the set voltage to the first or second input/output terminal of the latch depending on the data bit to be written; and an output switch device (280-1b,280-2b) for transferring onto the respective data line the read data bit temporarily stored into the latch in response to an output control signal (DO-1,DO-2), the output switch device having a first terminal coupled to one among the first and second input/output terminals of the latch, a second terminal connected to the respective data line and a control terminal receiving the output control signal.

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