公开(公告)号：ITMI20022629A1

公开(公告)日：2004-06-13

申请号：ITMI20022629

申请日：2002-12-12

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  RAVASIO ROBERTO

IPC: G06F13/00 ,  G06F13/42 ,  G11B20060101 ,  G11C7/10 ,  G11C7/22 ,  G11C16/32

公开(公告)号：ITTO20010529A1

公开(公告)日：2002-12-02

申请号：ITTO20010529

申请日：2001-06-01

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  ZANARDI STEFANO ,  PICCA MASSIMILIANO ,  RAVASIO ROBERTO

IPC: G06F11/10 ,  G06F12/00

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.

公开(公告)号：DE602004026707D1

公开(公告)日：2010-06-02

申请号：DE602004026707

申请日：2004-06-30

Applicant: ST MICROELECTRONICS SRL

Inventor： MARELLI ALESSIA ,  RAVASIO ROBERTO ,  MICHELONI RINO

IPC: H03M13/15 ,  G06F11/10

Abstract: The invention relates to a method and system for correcting errors in multilevel memories using binary BCH codes. The number of errors is estimated by analyzing the syndrome components (5). If the number of estimated errors is one, then simple decoding for a Hamming code is performed. Otherwise, conventional decoding of the BCH code is carried out (2,3). This avoids the computation of the error locator polynomial and its roots in the presence of only one error and, thus, reduces the average decoding complexity.

公开(公告)号：ITTO20010529D0

公开(公告)日：2001-06-01

申请号：ITTO20010529

申请日：2001-06-01

Applicant: ST MICROELECTRONICS SRL

Inventor： MICHELONI RINO ,  ZANARDI STEFANO ,  PICCA MASSIMILIANO ,  RAVASIO ROBERTO

IPC: G06F11/10 ,  G06F12/00

Abstract: A method for error control in multilevel memory cells storing a configurable number of bits. The error control is performed using an error-control code which operates, in the encoding phase, on b-bit binary strings made up of k symbols of r-bit data. When the memory cells store a number r of bits, a data symbol is formed only with the data bits stored in a memory cell. When the memory cells store a number s of bits smaller than r, a data symbol is formed with the data bits stored in a memory cell and with r-s bits having a pre-determined logic value, in which the data bits stored in the memory cell are arranged in the least significant part of the data symbol, and the r-s bits having a pre-determined logic value are arranged in the most significant part of the data symbol.