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    CIRCUIT AND METHOD FOR WRITING INTO MEMORY DISK BY BOOSTED VOLTAGE
    11.
    发明专利
    CIRCUIT AND METHOD FOR WRITING INTO MEMORY DISK BY BOOSTED VOLTAGE 失效

    公开(公告)号：JP2001101609A

    公开(公告)日：2001-04-13

    申请号：JP2000275203

    申请日：2000-09-11

    Applicant: ST MICROELECTRONICS INC

    Inventor： PATTI GUISEPPE ,  ALINI ROBERTO ,  PAKRISWAMY ELANGO

    IPC: G11B5/09 ,  G11B5/012 ,  G11B5/02

    Abstract: PROBLEM TO BE SOLVED: To provide an improved circuit and the method for driving a writing head of a disk storage device. SOLUTION: When the current flowing direction through the writing head is inverted from the 1st direction supplying the current to the writing head through a writing head terminal to the 2nd direction drawing out the current from the writing head through the writing head terminal, a bootstrap circuit and a current sync circuit are activated to enable the current to be quickly drawn out from the writing head.

    DEVICE AND METHOD FOR REDUCING THERMAL INTERFERENCE OF MR HEAD OF DISK DRIVE
    12.
    发明专利
    DEVICE AND METHOD FOR REDUCING THERMAL INTERFERENCE OF MR HEAD OF DISK DRIVE 失效

    公开(公告)号：JP2000163705A

    公开(公告)日：2000-06-16

    申请号：JP32907799

    申请日：1999-11-19

    Applicant: ST MICROELECTRONICS INC

    Inventor： PATTI GUISEPPE ,  LEE EUGENE C ,  ALINI ROBERTO

    IPC: G11B5/09 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02 ,  G11B20/10 ,  G11B20/24 ,  G11B27/36

    Abstract: PROBLEM TO BE SOLVED: To remove the ringing and unnecessary offset of a read signal by making resistance values equal to a 1st and a 2nd specific resistance value in response to a 1st and a 2nd control input and generating the 2nd control input in response to the detection of a thermal event. SOLUTION: An effective resistance value is given by a resistance R1 and the programmed resistance value of a resistance R1 and a variable resistance value circuit 132 and the cutoff frequency of a filter 112 varies as the resistance value of the variable resistance value circuit 132 varies. In a normal operation period of a read channel, the resistance value of the variable resistance value circuit 132 is relatively high impedance and the effective resistance value of the filter 112 becomes substantially equal to the resistance value of the resistance R1. When thermal variation is detected, the effective resistance value of the filter 112 decreases to increase the cutoff frequency. This effective resistance value decreases by programming the variable resistance value circuit 132 to a specific resistance value in response to the input signal from a control circuit 110.

    WRITE HEAD DRIVER CIRCUIT AND METHOD FOR WRITING TO MEMORY DISK
    13.
    发明专利
    WRITE HEAD DRIVER CIRCUIT AND METHOD FOR WRITING TO MEMORY DISK 审中-公开

    公开(公告)号：JP2003187402A

    公开(公告)日：2003-07-04

    申请号：JP2002327083

    申请日：2002-11-11

    Applicant: ST MICROELECTRONICS INC

    Inventor： VENCA ALESANDRO ,  POSAT BARIS ,  OZANOGLU KEMAL ,  ALINI ROBERTO

    IPC: G11B5/09 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02

    Abstract: PROBLEM TO BE SOLVED: To provide a circuit and a method which comparatively rapidly transition a current flowing through a write head during normal operating conditions, without generating capacitively coupled noise. SOLUTION: A drive voltage signal which will not have a common mode voltage level in a transition period among the normal operating conditions in the write head is supplied to the write head. That is, the drive voltage signal impressed to the writing head is substantially and entirely differential during the transition period of a write head current. A driver circuit has the terminal of the write head and a switching circuit, connected between reference voltage supply sources such as positive and negative voltage sources. The driver circuit has a timing circuit for generating a controlling signal which controls the switching circuit. COPYRIGHT: (C)2003,JPO

    DRIVER CIRCUIT OF WRITE HEAD FOR WRITING TO MEMORY DISK AND ITS METHOD
    14.
    发明专利
    DRIVER CIRCUIT OF WRITE HEAD FOR WRITING TO MEMORY DISK AND ITS METHOD 审中-公开

    公开(公告)号：JP2002123902A

    公开(公告)日：2002-04-26

    申请号：JP2001260774

    申请日：2001-08-30

    Applicant: ST MICROELECTRONICS INC

    Inventor： PATTI GUISEPPE ,  ALINI ROBERTO

    IPC: G11B5/09 ,  G11B5/00 ,  G11B5/012 ,  G11B5/02

    Abstract: PROBLEM TO BE SOLVED: To provide an improved method and the circuit for controlling a write head for a magnetic disk storage device. SOLUTION: When the flow direction of the current is reversed from the 1st direction in which the current is being supplied to the write head through a write head terminal to the 2nd direction in which the current is drawn out from the write head through the write head terminal, an appropriate pull-up device is activated during the period of specified time. A clamp device being connected to the pull-up device to be temporarily activated is activated after that, thereby the corresponding write head terminal is clamped to the intermediate voltage level at the steady state.

    18.
    发明专利
    未知

    公开(公告)号：DE69327053D1

    公开(公告)日：1999-12-23

    申请号：DE69327053

    申请日：1993-09-21

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MOLONEY DAVID ,  GADDUCCI PAOLO ,  BETTI GIORGIO ,  ALINI ROBERTO

    IPC: G11B20/10 ,  G11B20/14 ,  H03M5/06 ,  H03M5/14

    Abstract: In a decoder for decoding a serial data stream, employing an extracted base clock signal, synchronous with an input, coded, serial data stream, a fractionary frequency clock signal for sampling a decoded output data stream and a second fractionary clock signal for synthesizing a pre-decoded value produced by a first combinative logic network within a second combinative logic network to produce a decoded value that is sent to an output sampling flip-flop, a pipelined operation is implemented by momentarily storing the bits that are processed in the second combinative logic network and by anticipating of two full cycles of the synchronous base clock the processing by said first combinative network of the n-number of bits handled by the decoder. Each one of the two combinative logic networks is permitted to complete its decoding process within a full clock cycle in advance of the raising front of the outpunt sampling clock signal. With the same fabrication technology and therefore with the same propagation delay of the two combinative logic networks, the maximum operating spead may be doubled. A limited number of additional components are required to implement the pipelined operation of the invention.

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