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    Method of manufacturing an integrated semiconductor device comprising a floating gate field-effect transistor and a logic-field effect transistor, and corresponding device
    12.
    发明公开
    Method of manufacturing an integrated semiconductor device comprising a floating gate field-effect transistor and a logic-field effect transistor, and corresponding device 审中-公开
    制造具有浮置栅极和一个逻辑场效应晶体管的场效应晶体管的集成半导体器件的方法，和相应的布置

    公开(公告)号：EP0993036A1

    公开(公告)日：2000-04-12

    申请号：EP98830595.9

    申请日：1998-10-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Baldi, Livio ,  Maurelli, Alfonso

    IPC: H01L21/8239 ,  H01L27/105 ,  H01L21/8247 ,  H01L27/115

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539 ,  H01L27/11546

    Abstract: Method of manufacturing an integrated semiconductor device comprising at least one non-volatile floating gate memory cell (20) and at least one logic transistor (10). Said method comprises a first step of growing a first gate oxide layer (2) over a silicon substrate (1), a second step of depositing a first polysilicon layer (3) over the first gate oxide layer (2), a third step of selectively etching and removing the first polysilicon layer (3) in order to define the floating gate (31) of the memory cell (20), a fourth step of introducing dopant in order to obtain source (5) and drain (6) regions of the memory cell (20), a fifth step of depositing a dielectric layer (7), a sixth step of selectively etching and removing the dielectric layer (7) and the first polysilicon layer (3) in a region wherein the logic transistor (10) will be formed, a seventh step of depositing a second polysilicon layer (11), an eighth step of selectively etching and removing the second polysilicon layer (11) in order to define the gate (32) of the logic transistor (10) and the control gate (33) of the memory cell (20). Between the sixth step and the seventh step a first sub-step of removing the first gate oxide layer (2) in the region for the logic transistor (10), a second sub-step of growing a second oxide gate layer (9) over the region, the second gate oxide layer (9) being different from, eg. having a smaller thickness than that of the first gate oxide layer (2), are provided. A high voltage transistor (30) having a gate oxide constituted by said first gate oxide layer (2) and a gate electrode constituted by said first polysilicon layer (3) may furthermore be formed together with said memory cell (20) and said logic transistor (10).

    Abstract translation: 制造集成半导体器件的方法，包括至少一个非易失性浮栅存储器单元（20）和至少一个逻辑晶体管（10）。 所述方法包括生长第一栅氧化物层的第一步骤（2）在硅衬底（1），沉积第一多晶硅层（3）在所述第一栅氧化物层（2），第三步骤的第二步骤 选择性地蚀刻并以限定存储器单元的浮置栅极（31）（20），以获得源将掺杂剂引入的第四工序除去第一多晶硅层（3）（5）和漏区（6）的区域 存储器单元（20），沉积电介质层（7），选择性地蚀刻的第六步骤以及去除所述电介质层（7）和所述第一多晶硅层的第五步骤（3）的区域中worin逻辑晶体管（10 ）将被形成的，沉积第二多晶硅层（11），（在选择性地蚀刻的第八步骤，并且为了限定逻辑（10的栅极（32）去除第二多晶硅层11）晶体管的第七步骤），并 存储器单元的控制栅极（33）（20）。 第六步骤和第七步骤，用于所述逻辑晶体管（10），生长第二氧化物栅极层的第二子步骤中除去在该区域所述第一栅氧化层（2）的第一子步骤（9）之间过 的区域中，所述第二栅极氧化物层（9）不同于，具有比被设置（2）例如，第一栅极氧化物层的厚度较小.. 具有由所述第一栅氧化层（2）构成的栅氧化层和由所述第一多晶硅层（3）构成的栅极电极的高电压晶体管（30）可以进一步被一起与所述存储单元（20）和所述逻辑晶体管构成 （10）。

    Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process
    13.
    发明公开
    Matrix of memory cells fabricated by means of a self-aligned source process, comprising ROM memory cells, and related manufacturing process 失效
    通过自对准源方法（SAS）中制备存储单元阵列，包括只读存储单元（ROM），和它们的制备方法

    公开(公告)号：EP0957521A1

    公开(公告)日：1999-11-17

    申请号：EP98830282.4

    申请日：1998-05-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Baldi, Livio ,  Ghezzi, Paolo

    IPC: H01L27/112 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/11246 ,  H01L27/112

    Abstract: Matrix of memory cells formed by means of a method allowing for a self-alignment of the respective source region with the respective field oxide layer and the respective overlying polysilicon layer of each single cell of the matrix, the matrix comprising at least one first ROM memory cell (6) suitable for permanently storing a first logic level, associated to a respective row and a respective column of the matrix, said first cell comprising a silicon substrate (9) of a first conductivity type over which a first and a second insulation regions (3) are formed delimiting therebetween a longitudinal stripe, a gate element (2) extending transversally through the stripe from at least one side of the first isolation region to at least one side of the second isolation region, a third and a fourth regions (11,12) of a second conductivity type formed in the substrate (9) along the stripe, and means (3) adapted to prevent the formation of a conductive channel in the substrate (9), and at least a second ROM cell (5) for permanently storing a second logic level, identical to the first ROM (6) memory cell but not provided with said means (3).

    Abstract translation: 通过允许与respectivement场氧化物层和所述矩阵的每个单电池的respectivement覆多晶硅层的respectivement源极区的自对准的方法形成的存储器单元的矩阵，所述矩阵包括至少一个第一ROM存储器 细胞（6）适合于永久地存储第一逻辑电平，关联到respectivement行和矩阵的respectivement柱，所述第一电池，其包括硅衬底（9）的第一导电类型的在其上第一和第二绝缘区域 （3）形成的纵向条纹之间限定有，栅极元件（2）横向延伸穿过所述条纹从第一隔离区域的至少一侧，以所述第二隔离区，第三和第四区域中的至少一个侧面（ 11,12）在沿着所述条带中的基片（9）形成的第二导电类型，以及装置（3）angepasst以防止信道的形成的导电性基板（9），和至少一个 第二ROM单元（5）用于永久存储第二逻辑电平，相同于第一ROM（6）的存储单元，但不具有所述装置（3）。

    Currency note comprising an integrated circuit
    14.
    发明公开
    Currency note comprising an integrated circuit 无效
    纸币与集成电路

    公开(公告)号：EP0905657A1

    公开(公告)日：1999-03-31

    申请号：EP97830464.0

    申请日：1997-09-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Baldi, Livio

    IPC: G07D7/00

    CPC classification number: G06K19/07749 ,  G07D7/01

    Abstract: The present invention relates to a currency note (BN) provided with an identification and/or authentication element consisting of an integrated circuit (IC) which can store, securely in electronic form, accessible from outside, such information as: the value, serial number, issuer, and date of issuance.

    High voltage capacitor
    20.
    发明公开
    High voltage capacitor 失效
    Hochspannungskondensator

    公开(公告)号：EP0893831A1

    公开(公告)日：1999-01-27

    申请号：EP97830384.0

    申请日：1997-07-23

    Applicant: STMicroelectronics S.r.l.

    Inventor： Baldi, Livio ,  Ghezzi, Paolo ,  Maurelli, Alfonso

    IPC: H01L29/92 ,  H01L27/08

    CPC classification number: H01L28/60 ,  H01L27/0805 ,  H01L29/94

    Abstract: A high voltage capacitor (1), integratable monolithically on a semiconductor substrate (7) which accommodates a field oxide region (2) overlaid by a first layer of polycrystalline silicon (Poly 1) isolated from a second layer of polycrystalline silicon (Poly 2) by an interpoly dielectric layer (6), comprises two elementary capacitors (C1,C2) having a first common conductive plate (3) which is formed in the first layer of polycrystalline silicon (Poly 1). Each of these elementary capacitors has a second conductive plate (4,5) formed in the second layer of polycrystalline silicon (Poly 2) above the first plate (3), and includes said interpoly dielectric layer (6) as an isolation dielectric between the two plates.

    Abstract translation: 一种高电压电容器（1），其单片地集成在半导体衬底（7）上，该半导体衬底（7）容纳由第二多晶硅层（Poly 2）隔离的第一多晶硅层（Poly 1）所覆盖的场氧化物区域（2） 通过间隔电介质层（6），包括两个元件电容器（C1，C2），其具有形成在第一多晶硅层（Poly 1）中的第一公共导电板（3）。 这些元件电容器中的每一个具有形成在第一板（3）上方的多晶硅（Poly 2）的第二层中的第二导电板（4,5），并且包括作为隔离介电层之间的隔离介电层（6） 两块板。

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