公开(公告)号：EP1686591A1

公开(公告)日：2006-08-02

申请号：EP05100551.0

申请日：2005-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Sforzin, Marco ,  Del Gatto, Nicola ,  Ferrario, Marco ,  Confalonieri, Emanuele

IPC: G11C16/26 ,  G11C11/56

CPC classification number: G11C16/26

Abstract: A memory device (100) is proposed. The memory device includes a plurality of memory cells (Mc) each one for storing a value, at least one reference cell (Mr 0 -Mr 2 ), biasing means (115) for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage (Vc,Vr) having a substantially monotone time pattern, means (130) for detecting the reaching of a threshold value by a current (Ic,Ir) of each selected memory cell and of each reference cell, and means (145) for determining the value stored in each selected memory cell according to a temporal relation of the reaching of the threshold value by the currents of the selected memory cell and of the at least one reference cell. The biasing means includes means (305) for applying a predetermined biasing current (Ib) to the selected memory cells and to the at least one reference cell.

Abstract translation: 一种存储器装置（100）被提议。 所述存储器装置包括存储器单元的用于偏置一组选择的存储单元的多个（MC）每一个用于存储一个值，至少一个参考单元（先生0 -Mr 2），偏压装置（115）和所述至少一个 具有用于每个被选择的存储单元的电流（Ic，Ir）的各基准单元的检测的阈值的到达基本上单调时间图案，装置（130）的偏置电压（VC，VR）参考单元，和 装置（145），用于确定挖掘存储在每个选定存储器单元gemäß阈值的通过和所述至少一个参考单元的选定存储器单元的电流的到达的时间关系的值。 偏压装置包括用于将预定偏置电流（Ib），以所选择的存储器单元和所述至少一个参考蜂窝小区的装置（305）。

公开(公告)号：EP1653474A1

公开(公告)日：2006-05-03

申请号：EP05022651.3

申请日：2005-10-18

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Emanuele ,  Del Gatto, Nicola ,  Lisi, Carlo ,  Ferrario, Marco

IPC: G11C11/56 ,  G11C5/14 ,  G11C16/30

CPC classification number: G11C8/10 ,  G11C8/18 ,  G11C11/5628 ,  G11C16/10 ,  G11C2211/5621

Abstract: The present invention relates to a method for programming a multilevel memory of the flash EEPROM type comprising a matrix of cells grouped in memory words.
Advantageously according to the invention the method provides the simultaneous generation of a first programming voltage value (V PROG ) and a second verify voltage value (V VER ), suitable to bias word lines (WLS) of the above memory matrix, respectively during programming and verify operations of the memory itself.
The present invention also relates to a circuit implementing the above method.

Abstract translation: 本发明涉及一种用于编程闪存EEPROM类型的多级存储器的方法，包括分组在存储器字中的单元矩阵。 有利地，根据本发明，该方法提供了同时产生适于在编程期间偏置上述存储器矩阵的字线（WLS）的第一编程电压值（V PROG）和第二验证电压值（V VER），以及 验证内存本身的操作。 本发明还涉及实现上述方法的电路。

公开(公告)号：EP1176603A1

公开(公告)日：2002-01-30

申请号：EP00830529.4

申请日：2000-07-26

Applicant: STMicroelectronics S.r.l.

Inventor： Confalonieri, Emanuele ,  Bedarida, Lorenzo ,  Sali, Mauro ,  Bartoli, Simone

IPC: G11C16/30

CPC classification number: G11C16/30

Abstract: The memory comprises a matrix of cells (10), a charge pump (11), a voltage regulator, controllable connection elements (12) each connected between the output of the charge pump (11) and a column line of the matrix of cells, and means (14) for selectively activating the connection elements.
To arrange for the voltage of a cell in a predetermined biasing condition, for example, the programming condition, to be independent of temperature variations and of manufacturing and design parameters, the memory comprises a first element (12') equivalent to a connection element (12) and a second element (10') equivalent to a memory cell (10) in the predetermined biasing condition. These equivalent elements are connected in series with one another between the output terminal and the common terminal of the charge pump (11). The regulator (15, 17) is connected between the second equivalent element (10') and the input of the charge pump (11) in order to regulate the output voltage of the charge pump (11) in dependence on the voltage across the second equivalent element (10').

Abstract translation: 所述存储器包括单元的矩阵（10），一个电荷泵（11），电压调节器，可控制连接件（12），每个连接在所述电荷泵的输出端（11）和单元的矩阵的列线之间， 和装置（14），用于选择性激活所述连接元件。 安排在一个预定的偏状态的电池的电压，例如，编程条件，是独立的温度变化的和的制造和设计参数，所述存储器包括：第一元件（12“）等同于一个连接元件（ 12）以及等同于预定的偏状态的存储单元（10）的第二元件（10“）。 这些等效的元件被串联连接与所述输出端子和所述电荷泵（11）的公共端子之间彼此。 调节器（15，17），以便调节上横跨第二电压依赖的电荷泵（11）的输出电压连接在第二等效元件（10“）和所述电荷泵（11）的输入端之间 等效元件（10“）。