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    A content addressable memory cell
    11.
    发明公开
    A content addressable memory cell 有权
    关于可选内容存储单元

    公开(公告)号：EP2261928A3

    公开(公告)日：2011-04-20

    申请号：EP10183801.9

    申请日：2003-10-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC: G11C15/04 ,  G11C14/00

    CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    Abstract: A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    A content addressable memory cell
    12.
    发明公开
    A content addressable memory cell 有权
    内容可寻址存储单元

    公开(公告)号：EP2261928A2

    公开(公告)日：2010-12-15

    申请号：EP10183801.9

    申请日：2003-10-22

    Applicant: STMicroelectronics S.r.l. ,  Ovonyx Inc.

    Inventor： De Sandre, Guido ,  Bez, Roberto ,  Pellizzer, Fabio

    IPC: G11C15/04

    CPC classification number: G11C15/04 ,  G11C13/0004 ,  G11C14/00 ,  G11C14/009 ,  G11C15/046

    Abstract: A content addressable memory cell (105) for a non-volatile Content Addressable Memory (100), including non-volatile storage means (S1,S2,S) for storing a content digit, a selection input (WL i ;WL i ,BLP j ) for selecting the memory cell, a search input for receiving a search digit (BLR j ,BLL j ), and a comparison circuit arrangement for comparing the search digit to the content digit and for driving a match output (ML i ) of the memory cell so as to signal a match between the content digit and the search digit. The non-volatile storage means include at least one Phase-Change Memory element (S1,S2,S) for storing in a non-volatile way the respective content digit.

    Abstract translation: 一种用于非易失性内容可寻址存储器（100）的内容可寻址存储器单元（105），包括用于存储内容数字的非易失性存储装置（S1，S2，S），用于存储内容数字的选择输入（WLi; WLi，BLPj） 选择存储器单元，用于接收搜索数字（BLRj，BLLj）的搜索输入以及用于将搜索数字与内容数字进行比较并用于驱动存储器单元的匹配输出（MLi）以便发信号 内容数字和搜索数字之间的匹配。 非易失性存储装置包括至少一个用于以非易失性方式存储相应内容数字的相变存储器元件（S1，S2，S）。

    Column decoder for non-volatile memory devices, in particular of the phase-change type
    13.
    发明公开
    Column decoder for non-volatile memory devices, in particular of the phase-change type 有权
    SpaltendekodiererfürnichtflüchtigeSpeicher des Phasen-Übergangstyps

    公开(公告)号：EP2159802A1

    公开(公告)日：2010-03-03

    申请号：EP09168918.2

    申请日：2009-08-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Sandre, Guido ,  Pasotti, Marco

    IPC: G11C16/02 ,  G11C7/12 ,  G11C13/02

    CPC classification number: G11C13/0026 ,  G11C13/0004

    Abstract: Described herein is a column decoder (5) for a phase-change memory device (1; 1') provided with an array (2) of memory cells (3), a reading stage (6) for reading data contained in the memory cells (3), and a programming stage (7) for programming these data; the column decoder (5) selects and enables biasing of a bitline (BL) of the array (2) and generates a current path between the bitline (BL) and the reading stage (6; 6') or, alternatively, the programming stage (7), respectively during a reading or a programming operation of the contents of the memory cells. In the column decoder, a first decoder circuit (5a) generates a first current path between the bitline (BL) and the reading stage (6; 6'), and a second decoder circuit (5b), distinct and separate from the first decoder circuit (5a), generates a second current path, distinct from the first current path, between the bitline (BL) and the programming stage (7).

    Abstract translation: 这里描述了一种用于存储单元（3）阵列（2）的相变存储器件（1; 1'）的列解码器（5），用于读取包含在存储器单元 （3）和用于编程这些数据的编程阶段（7） 列解码器（5）选择并启用阵列（2）的位线（BL）的偏置，并产生位线（BL）和读取级（6; 6'）之间的电流路径，或者编程级 （7），分别在存储单元的内容的读取或编程操作期间。 在列解码器中，第一解码器电路（5a）产生位线（BL）和读取级（6; 6'）之间的第一电流路径，以及第二解码器电路（5b），其与第一解码器 电路（5a）在位线（BL）和编程级（7）之间生成与第一电流路径不同的第二电流路径。

    Row decoder for non-volatile memory devices, in particular of the phase-change type
    14.
    发明公开
    Row decoder for non-volatile memory devices, in particular of the phase-change type 有权
    ZeilendekodiererfürnichtflüchtigeSpeicher des Phasen-Übergangstyps

    公开(公告)号：EP2159800A1

    公开(公告)日：2010-03-03

    申请号：EP09168915.8

    申请日：2009-08-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： De Sandre, Guido

    IPC: G11C8/08 ,  G11C13/02

    CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0028

    Abstract: Described herein is a row decoder (5) for a phase-change memory device (1) provided with an array (2) of memory cells (3) organized according to a plurality of array wordlines (WL ) and array bitlines (BL); the row decoder (5) has a hierarchical architecture and has a global decoder (8; 8') that addresses a first (MWL_LV; MWL') and a second (MWL; MWL_WR) global wordline according to first address signals (GP, D); and at least one local decoder (9; 9'), which is operatively coupled to the global decoder (8; 8') and addresses a respective array wordline (WL ) according to the value of the first global wordline and the second global wordline and of second address signals (WLSEL, WLSELN_LV; WLSEL_SW). The local decoder (9; 9') has a first circuit branch (25, 26, 31; 40, 41) generating, when the first global wordline (MWL_LV; MWL') is addressed, a first current path between the array wordline (WL ) and a first biasing source (V DD ) during a reading operation; and a second circuit branch (32; 42) generating, when the second global wordline (MWL_LV; MWL') is addressed, a second current path, distinct from the first current path, between the array wordline (WL ) and a second biasing source (V CC ) during a programming operation.

    Abstract translation: 本文描述了一种用于相变存储器件（1）的行解码器（5），其具有根据多个阵列字线（WL）和阵列位线（WL）组织的存储器单元（3）的阵列（2） BL）; 行解码器（5）具有层次结构，并且具有根据第一地址信号（GP，D）寻址第一（MWL_LV; MWL'）和第二（MWL; MWL_WR）全局字线的全局解码器（8; 8' ）; 以及至少一个本地解码器（9; 9'），其可操作地耦合到所述全局解码器（8; 8'），并且根据所述第一全局字线的值来寻址相应的阵列字线（WL） 第二全局字线和第二地址信号（WLSEL，WLSELN_LV; WLSEL_SW）。 本地解码器（9; 9'）具有第一电路分支（25,26,31; 40,41），当第一全局字线（MWL_LV; MWL'）被寻址时，第一电路分支（25,26,31; 40,41）在阵列字线 WL）和第一偏置源（V DD）; 以及第二电路分支（32; 42），当所述第二全局字线（MWL_LV; MWL'）被寻址时，产生与所述第一电流路径不同的第二电流路径，所述第二电流路径在所述阵列字线（WL）和 第二偏置源（V CC）。

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