公开(公告)号：EP1324342A1

公开(公告)日：2003-07-02

申请号：EP01830827.0

申请日：2001-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： De Sandre, Guido ,  Poles, Marco ,  Iezzi, David ,  Pasotti, Marco

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C2211/5641

Abstract: The invention relates to a programming method of a multilevel memory cell able to store a plurality of bits in a plurality of levels (N), the method comprising at least a step of writing a logic value in the multilevel memory cell by setting one of the programming levels (LA) thereof, these levels being included in the plurality of levels (N), with respect to a reference level (LR) according to the symbol to be written and to a previous programming level. The writing step is repeated until a highest possible value (Lmax) for the levels (LS, LR) is reached.
The invention relates also to a multilevel memory device comprising a plurality of multilevel memory cells organised into sectors, split into a plurality of data units (UD) whereon a programming operation is performed in parallel according to the method of the invention.

Abstract translation: 本发明涉及能够存储多个电平（N）中的多个位的多电平存储器单元的编程方法，所述方法至少包括以下步骤：通过将所述多电平存储器单元 编程电平（LA），这些电平相对于根据要写入的符号的参考电平（LR）和先前的编程电平被包括在多个电平（N）中。 重复写入步骤直到达到电平（LS，LR）的最高可能值（Lmax）。 本发明还涉及一种多级存储器件，其包括被组织成扇区的多个多电平存储器单元，分成多个数据单元（UD），根据本发明的方法并行执行编程操作。

公开(公告)号：EP1220228B1

公开(公告)日：2008-12-24

申请号：EP00830866.0

申请日：2000-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  De Sandre, Guido ,  Guaitini, Giovanni ,  Iezzi, David ,  Poles, Marco ,  Rolandi, PierLuigi

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/28 ,  G11C16/04

CPC classification number: G11C16/34 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/28

公开(公告)号：EP1215679B1

公开(公告)日：2004-03-03

申请号：EP01129768.6

申请日：2001-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： De Sandre, Guido ,  Pasotti, Marco ,  Rolandi, Pier Luigi ,  Guaitini, Giovani ,  Iezzi, David ,  Poles, Marco

IPC: G11C11/56

CPC classification number: G11C11/5635 ,  G11C11/5621 ,  G11C11/5628 ,  G11C17/146

公开(公告)号：EP1435621A1

公开(公告)日：2004-07-07

申请号：EP02425809.7

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  De Sandre, Guido ,  Iezzi, David ,  Muzzi, Gilberto ,  Poles, Marco

IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

CPC classification number: G11C16/30 ,  G06F1/26 ,  G11C5/145

Abstract: The invention relates to an architecture for distributing supply voltages to a plurality of memory modules (Mod1, ..., ModN) supplied through a plurality of charge pump circuits (Pump1, ..., PumpM).
Advantageously according to the invention, the architecture for distributing supply voltages comprises a sorting block (11) bidirectionally-connected to the plurality of memory modules (Mod1, ..., ModN) from which it receives a plurality of power requests and it is capable of providing a sorting signal (ORD) of said power requests on the basis of a priority scale in order to drive the plurality of charge pump circuits (Pump1, , PumpM) and distribute convenient supply voltages (Vhigh1, ..., VhighN; Vneg1, ..., VnegN) to the plurality of memory modules (Mod1, ..., ModN). Moreover, this architecture is software-configurable.

Abstract translation: 本发明涉及一种用于向通过多个电荷泵电路（Pump1，...，PumpM）提供的多个存储器模块（Mod1，...，ModN）分配电源电压的架构。 有利地，根据本发明，用于分配电源电压的架构包括双向连接到多个存储器模块（Mod1，...，ModN）的分类块（11），从该存储器模块接收多个电力请求 并且能够基于优先级来提供所述功率请求的分类信号（ORD），以驱动多个电荷泵电路（Pump1，PumpM）并且分配方便的电源电压（Vhigh1，...） ，VhighN; Vneg1，...，VnegN）连接到多个存储器模块（Mod1，...，ModN）。 而且，这种架构是软件可配置的。

公开(公告)号：EP1215679A1

公开(公告)日：2002-06-19

申请号：EP01129768.6

申请日：2001-12-13

Applicant: STMicroelectronics S.r.l.

Inventor： De Sandre, Guido ,  Pasotti, Marco ,  Rolandi, Pier Luigi ,  Guaitini, Giovani ,  Iezzi, David ,  Poles, Marco

IPC: G11C11/56

CPC classification number: G11C11/5635 ,  G11C11/5621 ,  G11C11/5628 ,  G11C17/146

Abstract: The invention relates to a programming method for a multilevel memory cell able to store a plurality of bits in a plurality of levels (N), which method comprises the phases of:

initially programming (I) a cell threshold value (VthDATI) to a first set of levels [O;(m-1)] being (m) a submultiple of the plurality (N) of levels of the multilevel cell;
reprogramming without erasing (II) another set of levels [m;(2m-1)] containing the same number of levels (m) as the first set;
reiterating (N R - 1 times) the reprogramming without erasing phase (III,IV, ...) until the levels (N) of the multilevel cell are exhausted.

The invention makes also reference to a multilevel memory device of the type comprising a plurality. of multilevel memory cells organised into sectors, the sectors being themselves split into a plurality of data units (UD) wherein a data updating operation is performed in parallel, the data units (UD) being programmed by means of the programming method according to the invention.

Abstract translation: 本发明涉及一种能够存储多个级别（N）中的多个位的多级存储器单元的编程方法，该方法包括以下阶段：首先将单元阈值（VthDATI）编程（I）到第一 层级ÄO;（m-1）Ü是（m）多级单元的多（N）个级别中的一个子; 重新编程而不擦除（II）另一组水平Äm;（2m-1）Ü包含与第一组相同数量的水平（m）; 重复（NR-1次）重编程而不擦除相位（III，IV，...），直到多级单元的电平（N）耗尽。 本发明还涉及包括多个类型的多级存储器件。 的多级存储器单元被组织成扇区，扇区本身被分成多个数据单元（UD），其中并行执行数据更新操作，数据单元（UD）通过根据本发明的编程方法进行编程 。

公开(公告)号：EP1324342B1

公开(公告)日：2008-07-16

申请号：EP01830827.0

申请日：2001-12-28

Applicant: STMicroelectronics S.r.l.

Inventor： De Sandre, Guido ,  Poles, Marco ,  Iezzi, David ,  Pasotti, Marco

IPC: G11C11/56

CPC classification number: G11C11/5628 ,  G11C2211/5641

公开(公告)号：EP1435621B1

公开(公告)日：2007-07-11

申请号：EP02425809.7

申请日：2002-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  De Sandre, Guido ,  Iezzi, David ,  Muzzi, Gilberto ,  Poles, Marco

IPC: G11C5/14 ,  G11C16/30 ,  H02M3/07

CPC classification number: G11C16/30 ,  G06F1/26 ,  G11C5/145

公开(公告)号：EP1220228A1

公开(公告)日：2002-07-03

申请号：EP00830866.0

申请日：2000-12-29

Applicant: STMicroelectronics S.r.l.

Inventor： Pasotti, Marco ,  De Sandre, Guido ,  Guaitini, Giovanni ,  Iezzi, David ,  Poles, Marco ,  Rolandi, PierLuigi

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/28 ,  G11C16/04

CPC classification number: G11C16/34 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/28

Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.

Abstract translation: 这里描述了一种用于将数据存储在非易失性存储器的第一和第二存储单元中的方法。 存储方法设想通过在第一存储单元中设置第一阈值电压和与第二存储单元中的第一阈值电压不同的第二阈值电压来以差分方式对第一和第二存储单元进行编程，阈值电压 表示存储在存储单元本身中的数据的两个存储器单元。