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公开(公告)号：EP1220228B1
公开(公告)日：2008-12-24
申请号：EP00830866.0
申请日：2000-12-29
Applicant: STMicroelectronics S.r.l.
Inventor： Pasotti, Marco , De Sandre, Guido , Guaitini, Giovanni , Iezzi, David , Poles, Marco , Rolandi, PierLuigi
CPC classification number: G11C16/34 , G11C16/0441 , G11C16/10 , G11C16/28
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2.发明公开Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices 失效用于受控擦除存储器设备，尤其是模拟或值-闪速EEPROM阵列的方法
公开(公告)号：EP0932161A1
公开(公告)日：1999-07-28
申请号：EP98830024.0
申请日：1998-01-22
Applicant: STMicroelectronics S.r.l.
Inventor： Pasotti, Marco , Canegallo, Roberto , Chioffi, Ernestina , Guaitini, Giovanni , Lhermet, Frank , Rolandi, Pierluigi
CPC classification number: G11C16/3409 , G11C11/56 , G11C11/5621 , G11C11/5635 , G11C16/16 , G11C16/3404 , G11C16/3445 , G11C27/005
Abstract: The controlled erase method includes supplying (40) at least one erase pulse to cells (3) of a memory array (2); comparing (53) the threshold voltage of the erased cells with a low threshold value; selectively soft-programming (62) the erased cells which have a threshold voltage lower than the low threshold value; and verifying (42) whether the erased cells have a threshold voltage lower than a high threshold value, which is higher than the low threshold value. If at least one predetermined number of erased cells has a threshold voltage which is higher than the high threshold value, an erase pulse is applied (44) to all the cells and the steps of comparing, selectively soft-programming and verifying are repeated.
Abstract translation: 受控擦除方法包括提供（40）至少一个擦除脉冲到单元的存储器阵列的（3）（2）; 比较（53）所述擦除单元具有低阈值的阈值电压; 选择性地软编程（62）的擦除单元，其具有阈值电压低于低阈值低; 和验证（42）是否擦除单元具有阈值电压高于高阈值的情况下，所有这是比所述低阈值高。 如果擦除单元中的至少一个预定数量的具有阈值电压的所有比该高阈值时，以擦除脉冲施加（44）到所有的细胞和进行比较的步骤，选择性地软编程，并且重复验证。
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3.发明公开Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method 有权擦除和用于存储块并行重新写入电路，尤其是对于模拟快闪单元，和它们的操作
公开(公告)号：EP1065668A1
公开(公告)日：2001-01-03
申请号：EP99830381.2
申请日：1999-06-21
Applicant: STMicroelectronics S.r.l.
Inventor： Pasotti, Marco , Guaitini, Giovanni , Rolandi, Pier Luigi
Abstract: Circuit for erasing and rewriting blocks of memory cells and particularly of analog flash cells, characterized in that it comprises at least one row decoding circuit (5, 7) comprising at least two adder blocks (31), suitable to generate a row address signal (32), at least two decoder blocks (33), suitable to generate respective pluralities of signals (34, 35, 36, 37; 42, 43, 44, 45) identifying a respective sector of memory to be enabled, at least two shifter blocks (38), suitable to generate an address signal (48, 49) of another row to be enabled, at least two OR logic blocks (39), suitable to generate respective signals (40; 41) serving the purpose to simultaneously enable at least two rows of the memory matrix (1).
Abstract translation: 电路用于擦除和重写的存储单元和特别模拟闪存单元，在做了它包括至少一个行解码电路，其特征的块（5,7）包括至少两个加法器块（31），适合于生成的行地址信号（ 32），至少两个解码器块（33）适合于产生的信号（34，35，36，37 respectivement多个;启用识别的存储器中的扇区respectivement 42，43，44，45），至少两个移动器 块（38）适合于产生对另一行的地址信号（48，49）被使能，至少两个OR逻辑块（39）适于产生respectivement信号（40; 41）服务的目的为能够同时在 存储器矩阵的至少两排（1）。
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Patent Agency Ranking4.发明授权Method for controlled erasing memory devices, in particular analog and multi-level flash-EEPROM devices 失效用于受控擦除存储器设备，尤其是模拟或值-闪速EEPROM阵列的方法
公开(公告)号：EP0932161B1
公开(公告)日：2004-06-09
申请号：EP98830024.0
申请日：1998-01-22
Applicant: STMicroelectronics S.r.l.
Inventor： Pasotti, Marco , Canegallo, Roberto , Chioffi, Ernestina , Guaitini, Giovanni , Lhermet, Frank , Rolandi, Pierluigi
CPC classification number: G11C16/3409 , G11C11/56 , G11C11/5621 , G11C11/5635 , G11C16/16 , G11C16/3404 , G11C16/3445 , G11C27/005
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5.发明公开
公开(公告)号：EP1220228A1
公开(公告)日：2002-07-03
申请号：EP00830866.0
申请日：2000-12-29
Applicant: STMicroelectronics S.r.l.
Inventor： Pasotti, Marco , De Sandre, Guido , Guaitini, Giovanni , Iezzi, David , Poles, Marco , Rolandi, PierLuigi
CPC classification number: G11C16/34 , G11C16/0441 , G11C16/10 , G11C16/28
Abstract: Described herein is a method for storing a datum in a first and a second memory cells of a nonvolatile memory. The storage method envisages programming the first and second memory cells in a differential way, by setting a first threshold voltage in the first memory cell and a second threshold voltage different from the first threshold voltage in the second memory cell, the difference between the threshold voltages of the two memory cells representing a datum stored in the memory cells themselves.
Abstract translation: 这里描述了一种用于将数据存储在非易失性存储器的第一和第二存储单元中的方法。 存储方法设想通过在第一存储单元中设置第一阈值电压和与第二存储单元中的第一阈值电压不同的第二阈值电压来以差分方式对第一和第二存储单元进行编程，阈值电压 表示存储在存储单元本身中的数据的两个存储器单元。
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6.发明授权Erasing and parallel rewriting circuit for memory cell blocks, particularly for analog flash cells, and related operating method 有权擦除和用于存储块并行重新写入电路，尤其是对于模拟快闪单元，和它们的操作
公开(公告)号：EP1065668B1
公开(公告)日：2006-08-09
申请号：EP99830381.2
申请日：1999-06-21
Applicant: STMicroelectronics S.r.l.
Inventor： Pasotti, Marco , Guaitini, Giovanni , Rolandi, Pier Luigi
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7.发明授权Device for reading nonvolatile memory cells, in particular analog flash memory cells 有权安排用于读取非易失性存储器单元，尤其是闪速模拟存储器单元
公开(公告)号：EP0997912B1
公开(公告)日：2006-01-11
申请号：EP98830626.2
申请日：1998-10-20
Applicant: STMicroelectronics S.r.l.
Inventor： Pasotti, Marco , Canegallo, Roberto , Guaitini, Giovanni , Rolandi, Pier Luigi
CPC classification number: G11C16/34 , G11C7/16 , G11C11/5621 , G11C11/5642 , G11C16/26 , G11C27/005 , G11C2211/5642
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8.发明公开Device for reading nonvolatile memory cells, in particular analog flash memory cells 有权An ere ere ere en en en en en en en en en en en en en en en en en en en en
公开(公告)号：EP0997912A1
公开(公告)日：2000-05-03
申请号：EP98830626.2
申请日：1998-10-20
Applicant: STMicroelectronics S.r.l.
Inventor： Pasotti, Marco , Canegallo, Roberto , Guaitini, Giovanni , Rolandi, Pier Luigi
CPC classification number: G11C16/34 , G11C7/16 , G11C11/5621 , G11C11/5642 , G11C16/26 , G11C27/005 , G11C2211/5642
Abstract: The reading device (1) comprises an A/D converter (8) of n+m bits receiving an input signal (V1) correlated to the threshold voltage (VTH) of the memory cell (2), and supplying a binary output word (WT) of n+m bits. The A/D converter (8) is of a double conversion stage type (8), wherein a first A/D conversion stage (10) carries out a first analog/digital conversion of the input signal (V1), to supply at the output a first intermediate binary word (W1) of n bits, and the second A/D conversion stage (16) can be activated selectively to carry out a second analog/digital conversion of a difference signal (VD) correlated to the difference between the input signal (V1) and the value of the first intermediate binary word (W1). The second A/D conversion stage (16) generates at the output a second intermediate binary word (W2) of m bits supplied, with the first intermediate binary word (W1), to an adder (20) generating the binary output word (WT) of n+m bits.
Abstract translation: 读取装置（1）包括接收与存储单元（2）的阈值电压（VTH）相关的输入信号（V1）的n + m位的A / D转换器（8），并且提供二进制输出字 WT）n + m位。 A / D转换器（8）是双转换级（8），其中第一A / D转换级（10）执行输入信号（V1）的第一模/数转换，以在 输出n位的第一中间二进制字（W1），并且可以选择性地激活第二A / D转换级（16），以对与第一中间二进制字（W1）之间的差相关的差信号（VD）进行第二模/数转换 输入信号（V1）和第一中间二进制字（W1）的值。 第二A / D转换级（16）在输出端产生与第一中间二进制字（W1）一起提供的m位的第二中间二进制字（W2）到生成二进制输出字（WT）的加法器（20） ）n + m位。
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