公开(公告)号：EP0997913B1

公开(公告)日：2005-08-10

申请号：EP98830654.4

申请日：1998-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Riva, Marco ,  Rolandi, Paolo ,  Montanaro, Massimo

IPC: G11C29/00 ,  G11C11/56 ,  G06F11/20

CPC classification number: G11C29/50 ,  G06F2201/81 ,  G11C11/56 ,  G11C11/5642 ,  G11C2029/5006 ,  G11C2211/5634

Abstract: A method for testing virgin memory cells in a multilevel memory device which comprises a plurality of memory cells, the particularity of which consists of the fact that it comprises the steps of: reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not; determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell; the at least one reference memory cell being chosen with a gradually higher threshold; when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.

公开(公告)号：EP0997913A1

公开(公告)日：2000-05-03

申请号：EP98830654.4

申请日：1998-10-29

Applicant: STMicroelectronics S.r.l.

Inventor： Riva, Marco ,  Hollandi, Paolo ,  Montanaro, Massimo

IPC: G11C29/00 ,  G11C11/56 ,  G06F11/20

CPC classification number: G11C29/50 ,  G06F2201/81 ,  G11C11/56 ,  G11C11/5642 ,  G11C2029/5006 ,  G11C2211/5634

Abstract: A method for testing virgin memory cells in a multilevel memory device which comprises a plurality of memory cells, the particularity of which consists of the fact that it comprises the steps of:

reading the individual memory cells that constitute a memory device and comparing each one of these memory cells with at least one reference memory cell at a time, so as to determine whether the threshold of the memory cells is lower than the threshold of the at least one reference memory cell or not;
determining the number of the memory cells whose threshold is higher than the threshold of the at least one reference cell;
the at least one reference memory cell being chosen with a gradually higher threshold;
when the number of memory cells whose threshold is higher than a given reference threshold is found to be sufficiently lower than the number of redundancy memory cells provided in the memory device, assuming the given reference threshold as lower reference threshold for the memory device, determining a statistical distribution of the thresholds of the memory cells.

Abstract translation: 一种用于测试多层存储器件中的原始存储器单元的方法，其包括多个存储器单元，其特殊性包括以下事实：其包括以下步骤：读取构成存储器件的各个存储单元，并将 这些存储单元同时具有至少一个参考存储器单元，以便确定存储器单元的阈值是否低于至少一个参考存储器单元的阈值; 确定阈值高于所述至少一个参考小区的阈值的存储器单元的数量; 所述至少一个参考存储器单元被选择为具有逐渐更高的阈值; 当发现阈值高于给定参考阈值的存储单元的数量足够低于设置在存储装置中的冗余存储单元的数目时，假设给定参考阈值为存储器件的较低参考阈值，则确定 存储单元阈值的统计分布。

公开(公告)号：EP0905710A1

公开(公告)日：1999-03-31

申请号：EP97830484.8

申请日：1997-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Fontana, Marco ,  Montanaro, Massimo

IPC: G11C16/06 ,  G11C5/14 ,  G05F3/26

CPC classification number: G11C16/30 ,  G05F3/262 ,  G11C5/147

Abstract: The invention relates to a compensated voltage regulator (1) useful with programming circuitry for electrically programmable non-volatile memory cells in a cell matrix (3) which is divided in sectors (7), the regulator being of a type which includes a comparator (2) connected between first (Vpp) and second (GND) supply voltage references, and having:

a first input terminal (+) which is supplied by a reference voltage (Vref);
an output terminal (U) connected to the control terminal of an output MOS transistor (Mcasc) having a conduction terminal through which an output current (Iout) is passed and being connected to the memory cells by a program line (10);
a second input terminal (-), feedback connected to said program line (10).

A compensation block (20) is provided which is powered from said first voltage reference (Vpp) and has an input connected to both said output terminal (U) and said output transistor (Mcasc), and has an output connected to said output terminal (U) to duplicate a current (Iout*α) which is suitably attenuated with respect to the output current (Iout) and useful to modify the output voltage (Vg) of the comparator (2) included in the regulator.

Abstract translation: 本发明涉及一个补偿电压调节器（1），用于在一个单元矩阵电可编程的非易失性存储器单元以编程电路有用（3）所有被划分成扇区（7），一个类型，其包括比较器的所述调节器（ 2）连接的第一（VPP）和第二（GND）供应电压基准，并具有之间：第一输入端（+），它是由一个基准电压（Vref）提供; 在输出端（U）连接到输出MOS晶体管具有通过输出电流的哪个（LOUT）被传递并且被连接到由程序线（10）的存储器单元的导通端子（Mcasc）的控制端子; 第二输入端子（ - ），反馈连接到所述编程线（10）。 这是从所述第一电压基准（Vpp）为动力的，并且具有连接到两个所述输出端子（U）和所述输出晶体管（Mcasc）输入，并具有连接到所述输出端子输出（A补偿块（20）提供的所有 U）复制一个电流（Iout *阿尔法）所有其适当相对于所述输出电流衰减（I OUT）和有用的修改比较器包括在所述调节器（2）的输出电压（Vg）。

公开(公告)号：EP1160795B1

公开(公告)日：2007-12-19

申请号：EP00830393.5

申请日：2000-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: G11C16/28 ,  G11C11/56

CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5642 ,  G11C2211/5634

公开(公告)号：EP1124313B1

公开(公告)日：2006-01-25

申请号：EP00830088.1

申请日：2000-02-08

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: H02M3/07

CPC classification number: H02M3/07

公开(公告)号：EP1160794A1

公开(公告)日：2001-12-05

申请号：EP00830392.7

申请日：2000-05-31

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: G11C11/56 ,  G11C16/28

CPC classification number: G11C7/1072 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/28 ,  G11C2211/5634

Abstract: The invention relates to a circuit structure (1) for programming data in reference cells (3) of an electrically programmable/erasable integrated non-volatile memory device, comprising a matrix of multi-level memory cells and at least one corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell (3) is incorporated, along with other cells of the same type, to a reference cell sub-matrix (4) which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode.
The bit lines of the sub-matrix (4) branch off to a series of switches (9) which are individually operated by respective control signals REF(i) issued from a logic circuit (8) with the purpose of selectively connecting the bit lines to a single external I/O terminal (10) through a single addressing line (11) of the access DMA mode.

Abstract translation: 本发明涉及一种用于对电可编程/可擦除集成非易失性存储器件的参考单元（3）中的数据进行编程的电路结构（1），包括多级存储器单元的矩阵和至少一个对应的参考单元 在读取阶段期间与相应的存储器单元进行比较。 参考单元（3）与相同类型的其他单元一起并入参考单元子矩阵（4），该参考单元子矩阵在结构上独立于存储单元矩阵并且在DMA模式下从外部直接访问。 子矩阵（4）的位线分支到由逻辑电路（8）发出的相应控制信号REF（i）分别操作的一系列开关（9），目的是选择性地连接位线 通过访问DMA模式的单个寻址线（11）连接到单个外部I / O端子（10）。

公开(公告)号：EP1143454A1

公开(公告)日：2001-10-10

申请号：EP00830239.0

申请日：2000-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: G11C16/12

CPC classification number: G11C16/12

Abstract: The integrated device (100) comprises a PMOS transistor (101) and a voltage selector (1) having an output (6g) connected to the bulk terminal (101d) of the PMOS transistor (101). The voltage selector (1) comprises an input stage (2) supplying (2c) a supply voltage (Vdd) or a programming voltage (Vpp) according to whether the device (100) is in a reading step or in a programming step; a comparator (3) connected to the output (2c) of the input stage (2), receiving a boosted voltage (Vboost), and generating (3g) a first control signal (OC), the state whereof depends upon the comparison of the voltages at the inputs of the comparator (3); a logic circuit (4) connected to the output (3g) of the comparator (3) and generating a second control signal (VDDIS), the state whereof depends upon the state of the first control signal (OC) and of a third-level signal (VTL); and a switching circuit (6) controlled by the first control signal (OC), by the second control signal (VDDIS), and by the third-level signal (VTL) and supplying (6g) each time the highest among the supply voltage (Vdd), the boosted voltage (Vboost), and the programming voltage (Vpp).

Abstract translation: 集成器件（100）包括PMOS晶体管（101）和电压选择器（1），其具有连接到PMOS晶体管（101）的体积端子（101d）的输出（6g）。 电压选择器（1）包括根据装置（100）是处于读取步骤还是编程步骤中的（2c）供应电压（Vdd）或编程电压（Vpp）的输入级（2） 连接到输入级（2）的输出（2c）的比较器（3），接收升压电压（Vboost），并产生（3g）第一控制信号（OC），其状态取决于 比较器（3）输入端的电压; 连接到比较器（3）的输出（3g）并产生第二控制信号（VDDIS）的逻辑电路（4），其状态取决于第一控制信号（OC）的状态和第三级 信号（VTL）; 以及由第一控制信号（OC），第二控制信号（VDDIS）和第三电平信号（VTL）控制的开关电路（6），并且每次在电源电压（ Vdd），升压电压（Vboost）和编程电压（Vpp）。

公开(公告)号：EP1143451A1

公开(公告)日：2001-10-10

申请号：EP00830238.2

申请日：2000-03-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rolandi, Paolo ,  Montanaro, Massimo ,  Oddone, Giorgio

IPC: G11C5/14

CPC classification number: G11C5/145

Abstract: The charge pump (1) comprises a phase-generator circuit (6) generating phase signals (A, B) and comprising an oscillator circuit (12.1-12.3) supplying a clock signal (CK), a current-limitation circuit (24.1-24.3) to limit the current flowing in the oscillator circuit, and a control circuit (26') supplying on an output (32a) a control signal (V REF ) supplied to the current-limitation circuit. The control circuit (26') comprises a first current mirror (60) connected to a ground line (22), a second current mirror (62) connected to a supply line (20), a cascode structure (64), arranged between the first and the second current mirrors (60, 62) and connected to the output (32a) of the control circuit (26') to compensate the effects on the control signal (V REF ) caused by sharp relative variations between the potential (V DD ) of the supply line and the potential (V GND ) of the ground line, and a compensation circuit (70) to compensate the effects on the control signal (V REF ) caused by sharp relative variations between the potential (V DD ) of the supply line and the potential (V GND ) of the ground line and by slow variations in temperature.

Abstract translation: 电荷泵（1）包括产生相位信号（A，B）的相位发生器电路（6），并且包括提供时钟信号（CK）的振荡器电路（12.1-12.3），电流限制电路（24.1-24.3 ）以限制在振荡器电路中流动的电流，以及向输出（32a）提供提供给电流限制电路的控制信号（VREF）的控制电路（26'）。 控制电路（26'）包括连接到地线（22）的第一电流镜（60），连接到电源线（20）的第二电流镜（62），共源共栅结构（64） 第一和第二电流镜（60,62），并且连接到控制电路（26'）的输出端（32a），以补偿由控制信号（VREF）的电位（VDD）之间的尖锐相对变化引起的对控制信号 地线的电源线和电位（VGND）以及补偿电路（70），用于补偿由供电线的电位（VDD）与电位之间的尖锐相对变化引起的对控制信号（VREF）的影响 （VGND）和温度变化缓慢。